Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13948076

1

T2

18583

T3

14007

T4

73

full_word

55563030

1

T2

186712

T3

139163

T4

679

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	69510836	1			T2	205295		T3	153170		T4	752
auto[TlIntgErrCmd]	85	1			T105	10		T106	8		T107	5
auto[TlIntgErrData]	90	1			T105	5		T106	6		T107	9
auto[TlIntgErrBoth]	95	1			T105	5		T106	6		T107	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32038228

1

T2

102899

T3

76317

T4

368

auto[1]

37472878

1

T2

102396

T3

76853

T4

384

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6677039	1			T2	9232		T3	6989		T4	27
auto[TlIntgErrNone]	partial	auto[1]	7270789	1			T2	9351		T3	7018		T4	46
auto[TlIntgErrNone]	full_word	auto[0]	25361073	1			T2	93667		T3	69328		T4	341
auto[TlIntgErrNone]	full_word	auto[1]	30201935	1			T2	93045		T3	69835		T4	338
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T105	3		T106	1		T107	2
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T105	7		T106	6		T107	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T132	1		T130	1		T133	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T106	1		T107	1		T131	1
auto[TlIntgErrData]	partial	auto[0]	35	1			T105	1		T106	3		T107	4
auto[TlIntgErrData]	partial	auto[1]	48	1			T105	4		T106	3		T107	5
auto[TlIntgErrData]	full_word	auto[0]	3	1			T134	1		T135	1		T136	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T128	1		T131	1		T137	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T105	2		T106	1		T107	2
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T105	3		T106	5		T107	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T107	1		T127	1		T131	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T107	1		T130	2		T128	1