Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	517296	1			T5	14		T12	76		T13	29266
auto[1]	11195194	1			T2	46770		T3	32638		T4	317
auto[2]	444120	1			T5	15		T12	91		T13	24753
auto[3]	11136259	1			T2	46796		T3	32813		T4	347

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14898920	1			T2	78071		T3	53914		T4	541
auto[1]	2275064	1			T2	7464		T3	5469		T4	65
auto[2]	2267717	1			T2	7372		T3	5494		T4	53
auto[3]	3851168	1			T2	659		T3	574		T4	5

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9498157

1

T2

93486

T3

65392

T4

663

auto[1]

13794712

1

T2

80

T3

59

T4

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	267097	1			T5	12		T7	10		T123	25
auto[0]	auto[0]	auto[1]	27487	1			T12	1		T7	1		T123	2
auto[0]	auto[0]	auto[2]	27544	1			T5	2		T12	2		T7	1
auto[0]	auto[0]	auto[3]	7527	1			T12	72		T7	2		T142	11
auto[0]	auto[1]	auto[0]	3620196	1			T2	39045		T3	26904		T4	269
auto[0]	auto[1]	auto[1]	385410	1			T2	3504		T3	2701		T4	27
auto[0]	auto[1]	auto[2]	368079	1			T2	3831		T3	2726		T4	19
auto[0]	auto[1]	auto[3]	83486	1			T2	347		T3	275		T4	2
auto[0]	auto[2]	auto[0]	235017	1			T5	10		T7	3		T123	30
auto[0]	auto[2]	auto[1]	24203	1			T5	3		T12	8		T7	1
auto[0]	auto[2]	auto[2]	22160	1			T5	2		T12	1		T7	2
auto[0]	auto[2]	auto[3]	5945	1			T12	82		T142	6		T97	3
auto[0]	auto[3]	auto[0]	3588842	1			T2	38959		T3	26963		T4	271
auto[0]	auto[3]	auto[1]	366208	1			T2	3954		T3	2761		T4	38
auto[0]	auto[3]	auto[2]	381531	1			T2	3535		T3	2764		T4	34
auto[0]	auto[3]	auto[3]	87425	1			T2	311		T3	298		T4	3
auto[1]	auto[0]	auto[0]	6428	1			T13	926		T96	504		T97	337
auto[1]	auto[0]	auto[1]	27759	1			T13	4329		T96	2089		T97	1638
auto[1]	auto[0]	auto[2]	27746	1			T13	4314		T96	2034		T97	1705
auto[1]	auto[0]	auto[3]	125708	1			T12	1		T13	19697		T96	9333
auto[1]	auto[1]	auto[0]	3587283	1			T2	36		T3	26		T6	26
auto[1]	auto[1]	auto[1]	713674	1			T2	3		T3	3		T13	4338
auto[1]	auto[1]	auto[2]	709072	1			T2	3		T3	2		T6	1
auto[1]	auto[1]	auto[3]	1727994	1			T2	1		T3	1		T8	1
auto[1]	auto[2]	auto[0]	5625	1			T13	914		T96	293		T97	196
auto[1]	auto[2]	auto[1]	23926	1			T13	3899		T96	1241		T97	929
auto[1]	auto[2]	auto[2]	23095	1			T13	3599		T96	2305		T97	1763
auto[1]	auto[2]	auto[3]	104149	1			T13	16341		T96	9929		T97	7671
auto[1]	auto[3]	auto[0]	3588432	1			T2	31		T3	21		T4	1
auto[1]	auto[3]	auto[1]	706397	1			T2	3		T3	4		T6	4
auto[1]	auto[3]	auto[2]	708490	1			T2	3		T3	2		T6	5
auto[1]	auto[3]	auto[3]	1708934	1			T13	16580		T92	471		T96	11609