Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	308734330	125874	0	0
ctrl_regwen_rd_A	308734330	5635	0	0
exec_rd_A	308734330	4802	0	0
exec_regwen_rd_A	308734330	5770	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308734330	125874	0	0
T28	168742	4986	0	0
T29	108135	2887	0	0
T30	0	1140	0	0
T40	0	1975	0	0
T47	0	822	0	0
T48	0	1484	0	0
T49	0	3787	0	0
T50	0	5704	0	0
T51	0	1636	0	0
T52	0	611	0	0
T53	75238	0	0	0
T54	11003	0	0	0
T55	252380	0	0	0
T56	700812	0	0	0
T57	5980	0	0	0
T58	15097	0	0	0
T59	12208	0	0	0
T60	16526	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308734330	5635	0	0
T30	137075	202	0	0
T49	0	721	0	0
T51	0	252	0	0
T52	0	144	0	0
T108	0	217	0	0
T109	0	407	0	0
T110	0	463	0	0
T111	0	286	0	0
T112	0	825	0	0
T113	0	795	0	0
T114	348211	0	0	0
T115	60504	0	0	0
T116	11968	0	0	0
T117	31914	0	0	0
T118	4814	0	0	0
T119	56455	0	0	0
T120	614848	0	0	0
T121	2887	0	0	0
T122	63653	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308734330	4802	0	0
T30	137075	89	0	0
T49	0	748	0	0
T51	0	134	0	0
T52	0	153	0	0
T108	0	225	0	0
T109	0	404	0	0
T110	0	270	0	0
T111	0	245	0	0
T112	0	689	0	0
T113	0	612	0	0
T114	348211	0	0	0
T115	60504	0	0	0
T116	11968	0	0	0
T117	31914	0	0	0
T118	4814	0	0	0
T119	56455	0	0	0
T120	614848	0	0	0
T121	2887	0	0	0
T122	63653	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308734330	5770	0	0
T30	137075	139	0	0
T49	0	682	0	0
T51	0	322	0	0
T52	0	235	0	0
T108	0	286	0	0
T109	0	489	0	0
T110	0	506	0	0
T111	0	255	0	0
T112	0	797	0	0
T113	0	688	0	0
T114	348211	0	0	0
T115	60504	0	0	0
T116	11968	0	0	0
T117	31914	0	0	0
T118	4814	0	0	0
T119	56455	0	0	0
T120	614848	0	0	0
T121	2887	0	0	0
T122	63653	0	0	0