Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14595575	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59899102

1

T2

6688

T3

146767

T4

42727

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37130989	1			T2	3647		T3	80972		T4	118040
values[0x0]	17221724	1			T2	1755		T3	38709		T4	39848
values[0x1]	20141964	1			T2	1937		T3	41691		T4	77985

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7270688	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

67223989

1

T2

7042

T3

154065

T4

139447

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	281527	1			T4	893		T10	15		T11	28
valid_sources[0x01]	282660	1			T4	895		T10	22		T11	29
valid_sources[0x02]	321770	1			T2	3		T4	919		T10	24
valid_sources[0x03]	304866	1			T2	23		T4	929		T10	24
valid_sources[0x04]	291426	1			T2	63		T4	931		T10	18
valid_sources[0x05]	245128	1			T4	893		T10	20		T11	18
valid_sources[0x06]	326776	1			T2	37		T4	877		T10	25
valid_sources[0x07]	271310	1			T2	71		T4	942		T10	13
valid_sources[0x08]	293035	1			T2	13		T4	861		T10	18
valid_sources[0x09]	301692	1			T2	60		T4	951		T10	29
valid_sources[0x0a]	308822	1			T4	937		T10	29		T11	36
valid_sources[0x0b]	270663	1			T4	898		T10	28		T11	15
valid_sources[0x0c]	256942	1			T3	794		T4	971		T10	17
valid_sources[0x0d]	256403	1			T2	21		T4	866		T10	28
valid_sources[0x0e]	256846	1			T2	67		T4	938		T10	18
valid_sources[0x0f]	292508	1			T2	5		T4	904		T10	16
valid_sources[0x10]	300761	1			T4	953		T10	27		T11	22
valid_sources[0x11]	282283	1			T4	951		T10	21		T11	16
valid_sources[0x12]	276930	1			T2	59		T4	927		T10	19
valid_sources[0x13]	301225	1			T2	50		T4	814		T10	18
valid_sources[0x14]	270813	1			T2	20		T4	924		T10	29
valid_sources[0x15]	315004	1			T2	48		T4	965		T10	30
valid_sources[0x16]	321293	1			T2	2		T4	930		T10	22
valid_sources[0x17]	250957	1			T2	4		T4	862		T10	14
valid_sources[0x18]	293814	1			T2	51		T4	922		T10	21
valid_sources[0x19]	273125	1			T2	18		T4	923		T10	25
valid_sources[0x1a]	332744	1			T2	44		T4	901		T10	23
valid_sources[0x1b]	369176	1			T2	32		T4	958		T10	29
valid_sources[0x1c]	294287	1			T2	42		T4	872		T10	38
valid_sources[0x1d]	346871	1			T2	4		T4	959		T10	21
valid_sources[0x1e]	283416	1			T2	12		T4	917		T10	23
valid_sources[0x1f]	310515	1			T2	29		T4	867		T10	23
valid_sources[0x20]	246867	1			T4	910		T10	18		T11	25
valid_sources[0x21]	327030	1			T2	83		T3	39920		T4	952
valid_sources[0x22]	260324	1			T2	51		T3	1290		T4	910
valid_sources[0x23]	275890	1			T2	9		T4	934		T10	20
valid_sources[0x24]	314224	1			T3	4775		T4	960		T10	27
valid_sources[0x25]	329857	1			T2	72		T4	910		T10	20
valid_sources[0x26]	349101	1			T2	48		T4	875		T10	29
valid_sources[0x27]	363653	1			T4	883		T10	24		T11	21
valid_sources[0x28]	258507	1			T2	71		T4	968		T10	31
valid_sources[0x29]	278743	1			T2	15		T4	940		T10	19
valid_sources[0x2a]	289105	1			T2	80		T4	965		T10	15
valid_sources[0x2b]	245511	1			T4	926		T10	26		T11	26
valid_sources[0x2c]	259662	1			T4	907		T10	20		T11	22
valid_sources[0x2d]	264981	1			T2	51		T4	941		T10	18
valid_sources[0x2e]	322091	1			T2	11		T4	838		T10	32
valid_sources[0x2f]	258999	1			T2	10		T4	953		T10	20
valid_sources[0x30]	298386	1			T2	22		T4	938		T10	23
valid_sources[0x31]	244817	1			T4	840		T10	15		T11	18
valid_sources[0x32]	326141	1			T2	29		T4	910		T10	11
valid_sources[0x33]	304380	1			T4	925		T10	24		T11	23
valid_sources[0x34]	305209	1			T4	932		T10	26		T11	20
valid_sources[0x35]	321311	1			T2	45		T4	948		T10	20
valid_sources[0x36]	256209	1			T4	921		T10	23		T11	24
valid_sources[0x37]	348248	1			T4	888		T10	18		T11	24
valid_sources[0x38]	270155	1			T2	25		T4	925		T10	24
valid_sources[0x39]	268957	1			T2	77		T4	924		T10	24
valid_sources[0x3a]	263609	1			T4	953		T10	29		T11	28
valid_sources[0x3b]	292675	1			T2	41		T4	945		T10	28
valid_sources[0x3c]	286101	1			T2	15		T4	941		T10	19
valid_sources[0x3d]	268952	1			T2	1		T3	14		T4	897
valid_sources[0x3e]	348453	1			T2	45		T4	941		T10	19
valid_sources[0x3f]	336112	1			T2	70		T4	888		T10	18
valid_sources[0x40]	317298	1			T4	873		T10	23		T11	20
valid_sources[0x41]	321702	1			T2	58		T4	956		T10	21
valid_sources[0x42]	334002	1			T2	64		T4	893		T10	17
valid_sources[0x43]	293671	1			T2	38		T4	910		T10	27
valid_sources[0x44]	278814	1			T4	910		T10	28		T11	32
valid_sources[0x45]	287258	1			T2	14		T4	920		T10	21
valid_sources[0x46]	275574	1			T2	28		T4	907		T10	20
valid_sources[0x47]	278485	1			T4	921		T10	22		T11	25
valid_sources[0x48]	282634	1			T2	81		T4	891		T10	26
valid_sources[0x49]	300572	1			T2	178		T4	953		T10	16
valid_sources[0x4a]	292426	1			T4	871		T10	18		T11	15
valid_sources[0x4b]	237295	1			T2	114		T4	938		T10	21
valid_sources[0x4c]	268908	1			T3	5720		T4	923		T10	24
valid_sources[0x4d]	266672	1			T2	52		T4	983		T10	17
valid_sources[0x4e]	266634	1			T2	11		T4	951		T10	28
valid_sources[0x4f]	297908	1			T2	2		T4	840		T10	20
valid_sources[0x50]	330611	1			T2	106		T4	912		T10	16
valid_sources[0x51]	305321	1			T2	14		T4	952		T10	22
valid_sources[0x52]	292873	1			T4	926		T10	27		T11	22
valid_sources[0x53]	247301	1			T2	48		T4	926		T10	23
valid_sources[0x54]	284432	1			T2	92		T4	902		T10	23
valid_sources[0x55]	306994	1			T4	933		T10	22		T11	20
valid_sources[0x56]	294583	1			T2	90		T4	910		T10	16
valid_sources[0x57]	263097	1			T2	10		T4	878		T10	25
valid_sources[0x58]	306542	1			T2	94		T4	889		T10	22
valid_sources[0x59]	265134	1			T2	14		T4	917		T10	22
valid_sources[0x5a]	282110	1			T2	29		T4	820		T10	22
valid_sources[0x5b]	359637	1			T2	33		T4	891		T10	23
valid_sources[0x5c]	300890	1			T2	8		T4	933		T10	19
valid_sources[0x5d]	276670	1			T4	876		T10	15		T11	35
valid_sources[0x5e]	273485	1			T4	953		T10	18		T11	14
valid_sources[0x5f]	362003	1			T4	939		T10	19		T11	18
valid_sources[0x60]	301661	1			T2	9		T4	938		T10	20
valid_sources[0x61]	294611	1			T2	15		T3	2160		T4	918
valid_sources[0x62]	260946	1			T4	949		T10	19		T11	16
valid_sources[0x63]	274347	1			T2	12		T4	997		T10	29
valid_sources[0x64]	267891	1			T2	60		T4	949		T10	21
valid_sources[0x65]	305321	1			T4	982		T10	24		T11	26
valid_sources[0x66]	295794	1			T2	60		T4	908		T10	20
valid_sources[0x67]	301339	1			T2	99		T4	980		T10	21
valid_sources[0x68]	266869	1			T2	4		T4	897		T10	24
valid_sources[0x69]	340197	1			T2	15		T4	900		T10	24
valid_sources[0x6a]	339412	1			T2	1		T4	964		T10	32
valid_sources[0x6b]	249278	1			T2	16		T4	859		T10	16
valid_sources[0x6c]	261879	1			T4	962		T10	16		T11	23
valid_sources[0x6d]	284464	1			T4	883		T10	37		T11	21
valid_sources[0x6e]	265026	1			T4	980		T10	40		T11	33
valid_sources[0x6f]	356373	1			T2	63		T3	3571		T4	961
valid_sources[0x70]	259016	1			T2	38		T4	936		T10	23
valid_sources[0x71]	384924	1			T2	115		T4	947		T10	16
valid_sources[0x72]	328433	1			T2	61		T4	902		T10	22
valid_sources[0x73]	276501	1			T2	77		T4	891		T10	23
valid_sources[0x74]	329768	1			T4	868		T10	24		T11	29
valid_sources[0x75]	262708	1			T2	24		T4	908		T10	25
valid_sources[0x76]	300243	1			T2	13		T4	960		T10	19
valid_sources[0x77]	255223	1			T4	913		T10	13		T11	28
valid_sources[0x78]	279737	1			T2	114		T4	958		T10	18
valid_sources[0x79]	255766	1			T2	82		T4	898		T10	20
valid_sources[0x7a]	257897	1			T2	47		T4	970		T10	29
valid_sources[0x7b]	287663	1			T2	103		T4	945		T10	20
valid_sources[0x7c]	244417	1			T2	19		T4	892		T10	12
valid_sources[0x7d]	260094	1			T4	978		T10	34		T11	21
valid_sources[0x7e]	276554	1			T2	36		T4	939		T10	22
valid_sources[0x7f]	300546	1			T2	95		T4	945		T10	17
valid_sources[0x80]	331468	1			T2	90		T4	990		T10	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29836296

1

T2

3339

T3

73592

T4

21385

values[0x0]

all_enables

biggest_size

15031373

1

T2

1663

T3

36577

T4

10608

values[0x1]

all_enables

biggest_size

15031433

1

T2

1686

T3

36598

T4

10734

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35719	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

149518

1

T3

10

T11

1

T12

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	53717	1			T5	532		T9	80		T26	1178
values[0x0]	63511	1			T2	1		T3	19		T4	3
values[0x1]	68009	1			T1	1		T3	19		T4	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27176	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

158061

1

T3

11

T4

2

T11

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	610	1			T27	8		T43	7		T44	4
valid_sources[0x01]	561	1			T9	1		T27	23		T43	1
valid_sources[0x02]	654	1			T26	32		T27	31		T43	11
valid_sources[0x03]	703	1			T5	1		T27	30		T44	5
valid_sources[0x04]	755	1			T5	3		T26	4		T27	14
valid_sources[0x05]	980	1			T26	11		T27	11		T43	38
valid_sources[0x06]	702	1			T26	35		T27	12		T43	17
valid_sources[0x07]	1186	1			T26	211		T6	8		T27	11
valid_sources[0x08]	939	1			T5	63		T26	179		T27	33
valid_sources[0x09]	689	1			T9	1		T26	47		T6	8
valid_sources[0x0a]	773	1			T26	63		T27	10		T43	15
valid_sources[0x0b]	623	1			T9	1		T27	9		T43	8
valid_sources[0x0c]	810	1			T26	1		T27	7		T43	10
valid_sources[0x0d]	570	1			T5	44		T9	1		T65	1
valid_sources[0x0e]	1294	1			T12	2		T27	32		T43	14
valid_sources[0x0f]	772	1			T5	1		T27	19		T43	40
valid_sources[0x10]	773	1			T9	1		T27	1		T44	4
valid_sources[0x11]	796	1			T9	1		T26	3		T27	24
valid_sources[0x12]	635	1			T5	1		T26	1		T27	17
valid_sources[0x13]	763	1			T5	2		T26	3		T6	4
valid_sources[0x14]	657	1			T5	3		T27	2		T43	8
valid_sources[0x15]	834	1			T26	1		T27	15		T43	18
valid_sources[0x16]	609	1			T5	1		T9	1		T26	90
valid_sources[0x17]	573	1			T26	3		T27	19		T43	27
valid_sources[0x18]	823	1			T26	1		T6	14		T27	1
valid_sources[0x19]	742	1			T5	20		T9	1		T27	22
valid_sources[0x1a]	979	1			T27	16		T43	14		T44	5
valid_sources[0x1b]	819	1			T9	1		T26	1		T27	7
valid_sources[0x1c]	784	1			T3	4		T27	15		T43	39
valid_sources[0x1d]	625	1			T5	1		T27	15		T43	46
valid_sources[0x1e]	1045	1			T27	21		T43	12		T44	16
valid_sources[0x1f]	682	1			T27	35		T43	1		T44	6
valid_sources[0x20]	623	1			T5	1		T26	3		T27	3
valid_sources[0x21]	974	1			T5	1		T50	1		T26	1
valid_sources[0x22]	667	1			T5	10		T27	6		T43	28
valid_sources[0x23]	659	1			T9	1		T26	2		T27	7
valid_sources[0x24]	650	1			T33	1		T51	5		T27	35
valid_sources[0x25]	678	1			T9	1		T26	7		T27	21
valid_sources[0x26]	600	1			T26	2		T6	4		T27	12
valid_sources[0x27]	674	1			T5	1		T26	17		T27	10
valid_sources[0x28]	1078	1			T27	9		T43	12		T44	3
valid_sources[0x29]	785	1			T5	70		T27	14		T43	20
valid_sources[0x2a]	743	1			T27	22		T43	21		T44	4
valid_sources[0x2b]	677	1			T5	64		T27	21		T43	62
valid_sources[0x2c]	540	1			T5	6		T27	17		T43	15
valid_sources[0x2d]	544	1			T27	15		T44	7		T46	2
valid_sources[0x2e]	679	1			T42	6		T27	19		T43	1
valid_sources[0x2f]	588	1			T27	13		T43	18		T44	4
valid_sources[0x30]	576	1			T9	1		T27	7		T43	25
valid_sources[0x31]	596	1			T41	1		T26	1		T27	13
valid_sources[0x32]	565	1			T27	8		T44	2		T45	4
valid_sources[0x33]	626	1			T27	22		T43	34		T44	12
valid_sources[0x34]	589	1			T5	4		T26	21		T27	5
valid_sources[0x35]	652	1			T26	34		T27	26		T43	2
valid_sources[0x36]	651	1			T26	4		T27	23		T43	37
valid_sources[0x37]	544	1			T27	2		T43	1		T44	17
valid_sources[0x38]	790	1			T3	6		T9	1		T6	4
valid_sources[0x39]	592	1			T5	4		T9	1		T26	68
valid_sources[0x3a]	714	1			T27	18		T43	7		T44	4
valid_sources[0x3b]	604	1			T27	18		T43	6		T44	4
valid_sources[0x3c]	643	1			T3	6		T6	2		T23	11
valid_sources[0x3d]	988	1			T27	22		T43	22		T114	36
valid_sources[0x3e]	824	1			T26	13		T27	28		T43	8
valid_sources[0x3f]	818	1			T6	1		T27	14		T43	1
valid_sources[0x40]	746	1			T26	8		T27	9		T43	13
valid_sources[0x41]	949	1			T5	3		T9	1		T27	23
valid_sources[0x42]	909	1			T27	16		T43	5		T44	10
valid_sources[0x43]	622	1			T27	11		T43	14		T44	1
valid_sources[0x44]	746	1			T5	2		T26	70		T27	29
valid_sources[0x45]	822	1			T41	1		T27	18		T43	23
valid_sources[0x46]	829	1			T5	61		T26	51		T6	13
valid_sources[0x47]	907	1			T9	1		T37	17		T27	33
valid_sources[0x48]	729	1			T5	111		T26	56		T32	24
valid_sources[0x49]	715	1			T9	2		T27	16		T43	5
valid_sources[0x4a]	603	1			T27	20		T43	6		T121	6
valid_sources[0x4b]	647	1			T27	13		T43	33		T44	7
valid_sources[0x4c]	975	1			T5	2		T9	1		T27	7
valid_sources[0x4d]	939	1			T9	1		T26	169		T27	15
valid_sources[0x4e]	740	1			T5	30		T40	1		T26	4
valid_sources[0x4f]	603	1			T9	1		T26	4		T6	2
valid_sources[0x50]	758	1			T27	38		T43	21		T44	4
valid_sources[0x51]	692	1			T27	72		T43	3		T44	2
valid_sources[0x52]	703	1			T27	35		T43	8		T44	3
valid_sources[0x53]	660	1			T41	1		T26	37		T27	35
valid_sources[0x54]	574	1			T27	8		T43	19		T44	8
valid_sources[0x55]	671	1			T5	2		T9	1		T26	90
valid_sources[0x56]	905	1			T9	2		T26	116		T6	1
valid_sources[0x57]	656	1			T26	64		T27	5		T43	17
valid_sources[0x58]	683	1			T9	1		T26	36		T27	21
valid_sources[0x59]	706	1			T26	8		T27	13		T43	6
valid_sources[0x5a]	576	1			T9	2		T27	25		T43	4
valid_sources[0x5b]	638	1			T27	20		T43	28		T44	3
valid_sources[0x5c]	1227	1			T9	3		T26	111		T27	29
valid_sources[0x5d]	656	1			T41	1		T27	27		T43	14
valid_sources[0x5e]	668	1			T27	16		T43	28		T44	4
valid_sources[0x5f]	863	1			T26	25		T27	22		T43	30
valid_sources[0x60]	615	1			T9	1		T27	26		T43	12
valid_sources[0x61]	827	1			T5	156		T9	1		T26	39
valid_sources[0x62]	795	1			T26	65		T6	2		T27	16
valid_sources[0x63]	981	1			T26	149		T27	18		T43	49
valid_sources[0x64]	613	1			T9	1		T27	11		T43	20
valid_sources[0x65]	734	1			T26	2		T27	8		T43	18
valid_sources[0x66]	797	1			T26	145		T27	22		T43	19
valid_sources[0x67]	840	1			T6	1		T27	23		T43	21
valid_sources[0x68]	638	1			T26	1		T27	22		T43	8
valid_sources[0x69]	764	1			T9	2		T26	33		T6	4
valid_sources[0x6a]	760	1			T5	5		T27	13		T43	29
valid_sources[0x6b]	698	1			T4	7		T26	30		T27	11
valid_sources[0x6c]	598	1			T9	2		T26	1		T27	1
valid_sources[0x6d]	574	1			T5	1		T27	22		T43	20
valid_sources[0x6e]	514	1			T26	3		T27	8		T43	5
valid_sources[0x6f]	639	1			T26	1		T27	56		T43	1
valid_sources[0x70]	657	1			T27	17		T43	24		T44	5
valid_sources[0x71]	626	1			T3	1		T26	1		T27	28
valid_sources[0x72]	733	1			T10	1		T5	117		T26	2
valid_sources[0x73]	711	1			T26	104		T27	8		T43	12
valid_sources[0x74]	629	1			T3	1		T26	15		T27	4
valid_sources[0x75]	816	1			T9	1		T26	1		T27	31
valid_sources[0x76]	790	1			T5	1		T6	1		T27	3
valid_sources[0x77]	681	1			T27	25		T43	45		T44	16
valid_sources[0x78]	611	1			T6	2		T27	1		T43	4
valid_sources[0x79]	576	1			T27	39		T43	7		T44	17
valid_sources[0x7a]	586	1			T27	25		T43	1		T44	6
valid_sources[0x7b]	941	1			T5	14		T26	116		T27	6
valid_sources[0x7c]	688	1			T27	34		T43	10		T44	5
valid_sources[0x7d]	515	1			T27	12		T44	5		T45	4
valid_sources[0x7e]	576	1			T9	1		T6	2		T27	14
valid_sources[0x7f]	528	1			T26	1		T27	5		T43	6
valid_sources[0x80]	743	1			T26	61		T6	2		T27	29

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

40846

1

T5

467

T26

1093

T6

30

values[0x0]

all_enables

biggest_size

55341

1

T3

7

T11

1

T12

1

values[0x1]

all_enables

biggest_size

53331

1

T3

3

T5

619

T50

1