Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14316066

1

T2

651

T3

11632

T4

193146

full_word

54986778

1

T2

6688

T3

117348

T4

42727

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	69302534	1			T2	7339		T3	128980		T4	235873
auto[TlIntgErrCmd]	107	1			T94	2		T95	4		T96	3
auto[TlIntgErrData]	110	1			T94	5		T95	5		T96	4
auto[TlIntgErrBoth]	93	1			T94	3		T95	1		T96	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31855767

1

T2

3647

T3

48580

T4

118040

auto[1]

37447077

1

T2

3692

T3

80400

T4

117833

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6853493	1			T2	308		T3	4407		T4	96655
auto[TlIntgErrNone]	partial	auto[1]	7462289	1			T2	343		T3	7225		T4	96491
auto[TlIntgErrNone]	full_word	auto[0]	25002140	1			T2	3339		T3	44173		T4	21385
auto[TlIntgErrNone]	full_word	auto[1]	29984612	1			T2	3349		T3	73175		T4	21342
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T95	1		T96	1		T105	2
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T94	2		T95	1		T96	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T105	1		T103	1		T102	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T95	2		T102	1		T108	2
auto[TlIntgErrData]	partial	auto[0]	46	1			T94	3		T95	4		T96	3
auto[TlIntgErrData]	partial	auto[1]	55	1			T94	2		T96	1		T105	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T105	1		T104	1		T102	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T95	1		T106	1		T109	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T96	1		T103	5		T106	3
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T94	3		T95	1		T96	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T110	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T96	1		T111	1		T112	1