Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	731503	1			T4	14495		T5	532		T15	503
auto[1]	10353380	1			T2	167		T3	4084		T4	15608
auto[2]	614532	1			T4	14680		T5	362		T15	446
auto[3]	10250732	1			T2	185		T3	4019		T4	15984

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14505918	1			T2	254		T3	6694		T4	1211
auto[1]	2080447	1			T2	47		T3	710		T4	6505
auto[2]	2073005	1			T2	42		T3	643		T4	8684
auto[3]	3290777	1			T2	9		T3	56		T4	44367

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9184096

1

T2

351

T3

8097

T4

7

auto[1]

12766051

1

T2

1

T3

6

T4

60760

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	301217	1			T4	1		T5	436		T15	10
auto[0]	auto[0]	auto[1]	30992	1			T4	1		T5	54		T15	61
auto[0]	auto[0]	auto[2]	31086	1			T5	35		T15	75		T17	161
auto[0]	auto[0]	auto[3]	9643	1			T5	6		T15	357		T17	12
auto[0]	auto[1]	auto[0]	3470130	1			T2	117		T3	3379		T11	1854
auto[0]	auto[1]	auto[1]	369161	1			T2	34		T3	341		T4	2
auto[0]	auto[1]	auto[2]	352510	1			T2	12		T3	331		T11	376
auto[0]	auto[1]	auto[3]	76760	1			T2	4		T3	29		T11	86
auto[0]	auto[2]	auto[0]	261064	1			T5	272		T15	23		T17	1424
auto[0]	auto[2]	auto[1]	27031	1			T5	24		T15	71		T17	158
auto[0]	auto[2]	auto[2]	24202	1			T4	2		T5	60		T15	69
auto[0]	auto[2]	auto[3]	7066	1			T5	6		T15	282		T17	12
auto[0]	auto[3]	auto[0]	3433512	1			T2	136		T3	3311		T11	1822
auto[0]	auto[3]	auto[1]	348293	1			T2	13		T3	369		T11	392
auto[0]	auto[3]	auto[2]	362320	1			T2	30		T3	311		T11	392
auto[0]	auto[3]	auto[3]	79109	1			T2	5		T3	26		T4	1
auto[1]	auto[0]	auto[0]	12021	1			T4	486		T5	1		T17	4
auto[1]	auto[0]	auto[1]	53192	1			T4	2152		T39	1606		T7	1
auto[1]	auto[0]	auto[2]	53196	1			T4	2095		T39	1642		T7	2
auto[1]	auto[0]	auto[3]	240156	1			T4	9760		T39	7407		T89	14688
auto[1]	auto[1]	auto[0]	3508231	1			T3	2		T4	326		T11	2
auto[1]	auto[1]	auto[1]	626689	1			T4	2478		T12	1		T13	10
auto[1]	auto[1]	auto[2]	589533	1			T3	1		T4	1453		T13	3
auto[1]	auto[1]	auto[3]	1360366	1			T3	1		T4	11349		T12	1
auto[1]	auto[2]	auto[0]	10236	1			T4	292		T17	1		T39	225
auto[1]	auto[2]	auto[1]	44390	1			T4	1340		T39	984		T7	2
auto[1]	auto[2]	auto[2]	43587	1			T4	2375		T39	1563		T89	2742
auto[1]	auto[2]	auto[3]	196956	1			T4	10671		T15	1		T39	6916
auto[1]	auto[3]	auto[0]	3509507	1			T2	1		T3	2		T4	106
auto[1]	auto[3]	auto[1]	580699	1			T4	532		T11	1		T13	3
auto[1]	auto[3]	auto[2]	616571	1			T4	2759		T11	1		T12	1
auto[1]	auto[3]	auto[3]	1320721	1			T4	12586		T13	2		T51	54679