Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	340464278	146224	0	0
ctrl_regwen_rd_A	340464278	8243	0	0
exec_rd_A	340464278	7624	0	0
exec_regwen_rd_A	340464278	7480	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340464278	146224	0	0
T5	119490	2379	0	0
T9	22731	0	0	0
T14	15942	0	0	0
T15	25881	0	0	0
T16	13652	0	0	0
T17	139057	0	0	0
T26	0	4100	0	0
T27	0	4724	0	0
T33	1988	0	0	0
T37	367405	0	0	0
T43	0	4210	0	0
T44	0	1187	0	0
T45	0	1364	0	0
T46	0	1149	0	0
T47	0	1038	0	0
T48	0	1803	0	0
T49	0	1980	0	0
T50	3759	0	0	0
T51	424013	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340464278	8243	0	0
T5	119490	272	0	0
T9	22731	0	0	0
T14	15942	0	0	0
T15	25881	0	0	0
T16	13652	0	0	0
T17	139057	0	0	0
T33	1988	0	0	0
T37	367405	0	0	0
T44	0	276	0	0
T45	0	126	0	0
T47	0	262	0	0
T48	0	458	0	0
T50	3759	0	0	0
T51	424013	0	0	0
T97	0	456	0	0
T98	0	377	0	0
T99	0	649	0	0
T100	0	586	0	0
T101	0	472	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340464278	7624	0	0
T5	119490	196	0	0
T9	22731	0	0	0
T14	15942	0	0	0
T15	25881	0	0	0
T16	13652	0	0	0
T17	139057	0	0	0
T33	1988	0	0	0
T37	367405	0	0	0
T44	0	235	0	0
T45	0	121	0	0
T47	0	196	0	0
T48	0	426	0	0
T50	3759	0	0	0
T51	424013	0	0	0
T97	0	400	0	0
T98	0	307	0	0
T99	0	637	0	0
T100	0	607	0	0
T101	0	425	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340464278	7480	0	0
T5	119490	235	0	0
T9	22731	0	0	0
T14	15942	0	0	0
T15	25881	0	0	0
T16	13652	0	0	0
T17	139057	0	0	0
T33	1988	0	0	0
T37	367405	0	0	0
T44	0	332	0	0
T45	0	142	0	0
T47	0	207	0	0
T48	0	461	0	0
T50	3759	0	0	0
T51	424013	0	0	0
T97	0	332	0	0
T98	0	292	0	0
T99	0	529	0	0
T100	0	545	0	0
T101	0	401	0	0