Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13393141	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

56416514

1

T1

44

T2

113

T3

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34800429	1			T1	383		T2	841		T3	54
values[0x0]	16159042	1			T1	215		T2	371		T3	15
values[0x1]	18850184	1			T1	422		T2	719		T3	30

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6674512	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

63135143

1

T1

438

T2

874

T3

63

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	249336	1			T1	1		T2	2		T3	1
valid_sources[0x01]	244102	1			T1	9		T2	6		T4	1116
valid_sources[0x02]	272708	1			T1	4		T2	7		T3	1
valid_sources[0x03]	266219	1			T1	6		T3	1		T4	1295
valid_sources[0x04]	235135	1			T1	4		T4	1174		T8	30
valid_sources[0x05]	231689	1			T1	5		T2	8		T4	1222
valid_sources[0x06]	241878	1			T1	4		T4	1234		T8	27
valid_sources[0x07]	292136	1			T1	3		T2	5		T4	1349
valid_sources[0x08]	292018	1			T1	5		T2	15		T4	1200
valid_sources[0x09]	277114	1			T1	2		T2	4		T4	1310
valid_sources[0x0a]	305299	1			T1	8		T2	1		T4	1253
valid_sources[0x0b]	259761	1			T1	6		T2	13		T3	1
valid_sources[0x0c]	264995	1			T1	4		T2	26		T4	1284
valid_sources[0x0d]	250994	1			T1	6		T4	1334		T8	42
valid_sources[0x0e]	291876	1			T1	4		T2	6		T4	1228
valid_sources[0x0f]	259970	1			T1	3		T4	1281		T8	52
valid_sources[0x10]	272934	1			T1	7		T2	26		T4	1308
valid_sources[0x11]	281598	1			T1	5		T2	11		T4	1267
valid_sources[0x12]	239654	1			T1	6		T2	7		T4	1047
valid_sources[0x13]	405549	1			T1	1		T2	5		T4	1075
valid_sources[0x14]	241637	1			T1	6		T2	13		T4	1248
valid_sources[0x15]	263221	1			T2	13		T4	1237		T8	31
valid_sources[0x16]	275340	1			T1	6		T2	3		T4	1212
valid_sources[0x17]	254046	1			T1	4		T2	9		T3	1
valid_sources[0x18]	271463	1			T1	4		T2	1		T4	1190
valid_sources[0x19]	247469	1			T1	10		T2	4		T3	2
valid_sources[0x1a]	266084	1			T1	4		T2	18		T4	1131
valid_sources[0x1b]	249700	1			T1	5		T2	16		T4	1177
valid_sources[0x1c]	240917	1			T1	7		T2	2		T3	2
valid_sources[0x1d]	275142	1			T1	3		T3	1		T4	1285
valid_sources[0x1e]	259480	1			T1	6		T2	3		T4	1120
valid_sources[0x1f]	238777	1			T1	2		T2	2		T4	1288
valid_sources[0x20]	288832	1			T1	2		T2	5		T4	1347
valid_sources[0x21]	258011	1			T1	11		T2	10		T4	1244
valid_sources[0x22]	268364	1			T1	5		T2	1		T4	1349
valid_sources[0x23]	245722	1			T1	10		T2	4		T4	1271
valid_sources[0x24]	309825	1			T1	4		T2	4		T3	1
valid_sources[0x25]	228355	1			T1	4		T2	6		T3	1
valid_sources[0x26]	249330	1			T1	5		T4	1205		T8	34
valid_sources[0x27]	237191	1			T1	5		T4	1183		T8	52
valid_sources[0x28]	261675	1			T1	2		T2	19		T4	1272
valid_sources[0x29]	249654	1			T1	2		T2	21		T4	1069
valid_sources[0x2a]	262733	1			T1	6		T2	2		T4	1232
valid_sources[0x2b]	285743	1			T1	4		T4	1377		T8	37
valid_sources[0x2c]	284225	1			T1	1		T2	5		T3	1
valid_sources[0x2d]	290289	1			T1	1		T2	2		T4	1127
valid_sources[0x2e]	249524	1			T1	2		T2	16		T3	1
valid_sources[0x2f]	277269	1			T1	5		T2	10		T4	1206
valid_sources[0x30]	229807	1			T1	5		T4	1190		T8	27
valid_sources[0x31]	241461	1			T1	3		T3	1		T4	974
valid_sources[0x32]	251597	1			T1	3		T2	23		T4	1216
valid_sources[0x33]	262141	1			T1	4		T3	2		T4	1194
valid_sources[0x34]	242525	1			T1	5		T2	9		T4	1177
valid_sources[0x35]	283275	1			T1	2		T3	1		T4	1159
valid_sources[0x36]	236498	1			T1	2		T2	10		T3	1
valid_sources[0x37]	240374	1			T1	3		T2	3		T4	1055
valid_sources[0x38]	259064	1			T1	4		T2	2		T3	2
valid_sources[0x39]	342273	1			T1	2		T2	15		T3	2
valid_sources[0x3a]	241372	1			T1	5		T2	1		T4	1156
valid_sources[0x3b]	240541	1			T1	9		T2	18		T4	1433
valid_sources[0x3c]	270859	1			T1	6		T3	1		T4	1224
valid_sources[0x3d]	240458	1			T1	5		T2	1		T3	1
valid_sources[0x3e]	284166	1			T1	5		T2	12		T4	1347
valid_sources[0x3f]	272152	1			T1	6		T2	4		T4	1262
valid_sources[0x40]	290117	1			T1	4		T2	13		T4	1125
valid_sources[0x41]	254329	1			T1	8		T2	2		T4	1218
valid_sources[0x42]	257977	1			T1	4		T2	2		T3	1
valid_sources[0x43]	300393	1			T1	3		T2	10		T3	2
valid_sources[0x44]	295281	1			T1	2		T2	1		T3	1
valid_sources[0x45]	259985	1			T1	4		T2	6		T4	1130
valid_sources[0x46]	248358	1			T1	2		T2	1		T3	1
valid_sources[0x47]	284149	1			T1	6		T2	16		T3	2
valid_sources[0x48]	305392	1			T1	3		T2	8		T4	1159
valid_sources[0x49]	234043	1			T1	1		T4	1200		T8	49
valid_sources[0x4a]	290598	1			T1	2		T2	9		T4	1261
valid_sources[0x4b]	268780	1			T2	10		T4	1052		T8	36
valid_sources[0x4c]	239544	1			T1	3		T2	4		T4	1150
valid_sources[0x4d]	279101	1			T1	3		T2	6		T4	1313
valid_sources[0x4e]	341181	1			T1	4		T2	7		T4	1232
valid_sources[0x4f]	263480	1			T1	6		T2	2		T3	1
valid_sources[0x50]	343467	1			T1	2		T3	1		T4	1262
valid_sources[0x51]	315997	1			T1	6		T2	28		T4	1237
valid_sources[0x52]	278261	1			T1	1		T4	1205		T8	40
valid_sources[0x53]	316491	1			T1	2		T2	8		T4	1214
valid_sources[0x54]	283634	1			T1	2		T2	13		T4	1175
valid_sources[0x55]	241477	1			T1	4		T3	1		T4	1289
valid_sources[0x56]	265571	1			T1	3		T4	1181		T8	48
valid_sources[0x57]	355218	1			T1	7		T2	21		T4	1275
valid_sources[0x58]	230458	1			T1	3		T2	11		T3	1
valid_sources[0x59]	235138	1			T1	5		T2	18		T4	1116
valid_sources[0x5a]	300026	1			T1	3		T2	30		T4	1312
valid_sources[0x5b]	271927	1			T1	6		T2	18		T4	1099
valid_sources[0x5c]	267764	1			T1	4		T2	2		T3	1
valid_sources[0x5d]	306596	1			T1	2		T2	15		T4	1460
valid_sources[0x5e]	231611	1			T1	7		T2	21		T4	1159
valid_sources[0x5f]	257235	1			T1	1		T2	25		T3	1
valid_sources[0x60]	268127	1			T2	13		T3	1		T4	1229
valid_sources[0x61]	241364	1			T1	5		T2	7		T4	1078
valid_sources[0x62]	273735	1			T1	6		T4	1259		T8	31
valid_sources[0x63]	239081	1			T1	1		T2	14		T4	1247
valid_sources[0x64]	292917	1			T1	3		T2	10		T4	1229
valid_sources[0x65]	330514	1			T1	3		T3	1		T4	1062
valid_sources[0x66]	239547	1			T1	9		T2	9		T4	1319
valid_sources[0x67]	274588	1			T1	6		T2	6		T4	1208
valid_sources[0x68]	243742	1			T1	4		T2	15		T3	1
valid_sources[0x69]	233116	1			T1	5		T4	1172		T8	46
valid_sources[0x6a]	241257	1			T1	4		T2	10		T4	1315
valid_sources[0x6b]	263021	1			T1	1		T2	12		T4	1266
valid_sources[0x6c]	240222	1			T1	6		T2	30		T3	1
valid_sources[0x6d]	250454	1			T1	4		T2	1		T4	1239
valid_sources[0x6e]	276616	1			T1	2		T2	8		T4	1421
valid_sources[0x6f]	320111	1			T1	3		T2	1		T4	1106
valid_sources[0x70]	272338	1			T1	2		T2	5		T4	1174
valid_sources[0x71]	277478	1			T1	6		T4	1089		T8	22
valid_sources[0x72]	241164	1			T1	2		T2	12		T4	1266
valid_sources[0x73]	253155	1			T1	2		T2	26		T4	1308
valid_sources[0x74]	266964	1			T1	2		T4	1134		T8	40
valid_sources[0x75]	291500	1			T1	1		T2	11		T4	1174
valid_sources[0x76]	277222	1			T1	2		T2	5		T4	1212
valid_sources[0x77]	288293	1			T1	1		T2	18		T4	1335
valid_sources[0x78]	255131	1			T1	3		T2	5		T4	1144
valid_sources[0x79]	276460	1			T1	5		T2	10		T4	1160
valid_sources[0x7a]	276413	1			T1	2		T2	12		T3	1
valid_sources[0x7b]	304791	1			T1	5		T2	2		T4	1147
valid_sources[0x7c]	255736	1			T1	7		T2	1		T3	1
valid_sources[0x7d]	306787	1			T1	9		T3	1		T4	1154
valid_sources[0x7e]	281680	1			T1	4		T2	2		T3	2
valid_sources[0x7f]	310824	1			T1	3		T2	7		T4	1093
valid_sources[0x80]	270114	1			T1	2		T2	2		T4	1249

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28110777

1

T1

2

T2

9

T3

6

values[0x0]

all_enables

biggest_size

14149237

1

T1

26

T2

65

T3

4

values[0x1]

all_enables

biggest_size

14156500

1

T1

16

T2

39

T3

6

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32350	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

125558

1

T9

1

T5

37

T12

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	46277	1			T5	38		T6	24		T15	5
values[0x0]	54265	1			T2	1		T3	1		T4	1
values[0x1]	57366	1			T1	1		T4	3		T8	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24938	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

132970

1

T4

1

T8

1

T9

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	484	1			T5	1		T29	1		T30	3
valid_sources[0x01]	462	1			T18	1		T29	2		T150	1
valid_sources[0x02]	791	1			T5	1		T33	4		T34	7
valid_sources[0x03]	436	1			T138	1		T33	11		T144	4
valid_sources[0x04]	584	1			T1	1		T29	1		T33	15
valid_sources[0x05]	764	1			T15	1		T45	1		T33	7
valid_sources[0x06]	477	1			T6	2		T29	1		T33	4
valid_sources[0x07]	855	1			T15	1		T7	14		T29	2
valid_sources[0x08]	471	1			T30	1		T33	14		T151	6
valid_sources[0x09]	613	1			T7	6		T29	1		T30	1
valid_sources[0x0a]	541	1			T63	1		T152	4		T33	9
valid_sources[0x0b]	586	1			T5	1		T12	14		T33	10
valid_sources[0x0c]	686	1			T5	1		T62	55		T152	2
valid_sources[0x0d]	512	1			T63	4		T33	20		T151	4
valid_sources[0x0e]	511	1			T6	1		T63	1		T33	6
valid_sources[0x0f]	681	1			T5	1		T6	1		T99	1
valid_sources[0x10]	708	1			T33	36		T151	3		T153	2
valid_sources[0x11]	460	1			T63	2		T30	2		T137	2
valid_sources[0x12]	487	1			T33	5		T144	17		T34	5
valid_sources[0x13]	493	1			T63	2		T45	1		T33	6
valid_sources[0x14]	808	1			T63	1		T154	33		T33	13
valid_sources[0x15]	521	1			T6	3		T29	1		T33	20
valid_sources[0x16]	808	1			T32	24		T33	7		T34	3
valid_sources[0x17]	510	1			T15	1		T30	1		T33	16
valid_sources[0x18]	990	1			T30	1		T137	1		T33	5
valid_sources[0x19]	609	1			T5	1		T138	2		T33	9
valid_sources[0x1a]	493	1			T33	16		T34	4		T49	2
valid_sources[0x1b]	674	1			T30	1		T33	5		T34	8
valid_sources[0x1c]	794	1			T29	2		T137	1		T58	8
valid_sources[0x1d]	492	1			T6	1		T17	2		T137	1
valid_sources[0x1e]	642	1			T29	1		T33	23		T59	1
valid_sources[0x1f]	636	1			T5	1		T29	1		T138	1
valid_sources[0x20]	571	1			T5	1		T63	1		T32	3
valid_sources[0x21]	801	1			T63	2		T30	1		T138	1
valid_sources[0x22]	526	1			T6	2		T138	1		T33	14
valid_sources[0x23]	509	1			T5	1		T33	31		T34	3
valid_sources[0x24]	644	1			T63	1		T30	3		T43	1
valid_sources[0x25]	685	1			T7	21		T138	2		T33	8
valid_sources[0x26]	516	1			T32	8		T33	13		T151	2
valid_sources[0x27]	704	1			T5	1		T152	1		T138	1
valid_sources[0x28]	605	1			T15	1		T20	1		T32	7
valid_sources[0x29]	512	1			T29	3		T33	25		T34	6
valid_sources[0x2a]	633	1			T138	1		T137	1		T32	12
valid_sources[0x2b]	435	1			T63	1		T138	1		T33	13
valid_sources[0x2c]	634	1			T5	1		T63	2		T33	11
valid_sources[0x2d]	1004	1			T14	1		T41	21		T33	17
valid_sources[0x2e]	836	1			T10	1		T6	1		T30	1
valid_sources[0x2f]	718	1			T6	2		T63	1		T33	5
valid_sources[0x30]	687	1			T63	1		T30	3		T33	25
valid_sources[0x31]	792	1			T8	2		T58	2		T33	15
valid_sources[0x32]	604	1			T76	1		T33	19		T151	1
valid_sources[0x33]	764	1			T56	1		T33	21		T151	1
valid_sources[0x34]	456	1			T138	1		T33	2		T34	3
valid_sources[0x35]	933	1			T5	1		T33	5		T144	3
valid_sources[0x36]	513	1			T29	1		T138	1		T33	9
valid_sources[0x37]	535	1			T29	1		T33	2		T144	15
valid_sources[0x38]	619	1			T5	2		T138	1		T33	29
valid_sources[0x39]	829	1			T30	1		T45	2		T138	2
valid_sources[0x3a]	504	1			T30	2		T152	1		T57	4
valid_sources[0x3b]	832	1			T32	15		T58	4		T33	17
valid_sources[0x3c]	496	1			T30	1		T33	14		T34	2
valid_sources[0x3d]	643	1			T5	1		T63	2		T30	1
valid_sources[0x3e]	791	1			T5	1		T14	1		T29	1
valid_sources[0x3f]	597	1			T6	1		T152	2		T33	7
valid_sources[0x40]	584	1			T155	1		T33	8		T25	1
valid_sources[0x41]	724	1			T33	8		T34	5		T48	3
valid_sources[0x42]	600	1			T5	1		T63	1		T42	1
valid_sources[0x43]	539	1			T5	1		T30	1		T33	12
valid_sources[0x44]	386	1			T63	2		T45	1		T138	1
valid_sources[0x45]	684	1			T5	1		T6	1		T33	12
valid_sources[0x46]	660	1			T14	2		T33	16		T34	3
valid_sources[0x47]	551	1			T152	1		T33	8		T151	1
valid_sources[0x48]	530	1			T29	1		T55	3		T33	9
valid_sources[0x49]	523	1			T5	1		T6	1		T30	1
valid_sources[0x4a]	517	1			T5	1		T30	1		T33	7
valid_sources[0x4b]	557	1			T84	1		T138	1		T32	1
valid_sources[0x4c]	536	1			T63	2		T30	1		T84	1
valid_sources[0x4d]	588	1			T2	1		T58	5		T33	3
valid_sources[0x4e]	640	1			T5	1		T6	1		T18	2
valid_sources[0x4f]	586	1			T14	1		T63	1		T156	1
valid_sources[0x50]	601	1			T14	1		T63	1		T29	1
valid_sources[0x51]	479	1			T76	1		T138	1		T33	11
valid_sources[0x52]	555	1			T5	1		T16	9		T138	1
valid_sources[0x53]	470	1			T15	1		T29	1		T47	1
valid_sources[0x54]	515	1			T32	10		T33	22		T144	5
valid_sources[0x55]	506	1			T5	2		T15	1		T45	2
valid_sources[0x56]	576	1			T157	1		T15	1		T33	8
valid_sources[0x57]	694	1			T29	2		T84	1		T32	1
valid_sources[0x58]	643	1			T5	1		T20	2		T33	7
valid_sources[0x59]	665	1			T5	1		T94	1		T138	1
valid_sources[0x5a]	512	1			T28	42		T20	2		T57	11
valid_sources[0x5b]	1044	1			T63	2		T30	1		T45	1
valid_sources[0x5c]	723	1			T6	1		T14	1		T29	1
valid_sources[0x5d]	650	1			T20	1		T33	12		T151	3
valid_sources[0x5e]	598	1			T5	1		T33	17		T34	7
valid_sources[0x5f]	615	1			T6	1		T30	1		T152	1
valid_sources[0x60]	657	1			T33	10		T34	5		T158	1
valid_sources[0x61]	779	1			T99	1		T20	3		T33	17
valid_sources[0x62]	523	1			T5	1		T152	1		T33	12
valid_sources[0x63]	490	1			T29	2		T30	1		T152	1
valid_sources[0x64]	795	1			T5	1		T18	1		T30	2
valid_sources[0x65]	655	1			T63	2		T137	1		T58	1
valid_sources[0x66]	519	1			T5	1		T63	3		T32	3
valid_sources[0x67]	608	1			T159	2		T58	1		T33	20
valid_sources[0x68]	513	1			T5	1		T64	2		T63	1
valid_sources[0x69]	547	1			T6	1		T76	1		T15	1
valid_sources[0x6a]	642	1			T6	3		T14	1		T138	1
valid_sources[0x6b]	538	1			T18	1		T14	1		T63	1
valid_sources[0x6c]	524	1			T29	2		T152	1		T137	1
valid_sources[0x6d]	626	1			T6	1		T33	24		T144	3
valid_sources[0x6e]	801	1			T29	1		T20	2		T32	13
valid_sources[0x6f]	503	1			T7	14		T29	1		T58	3
valid_sources[0x70]	576	1			T5	1		T45	3		T33	8
valid_sources[0x71]	774	1			T29	1		T28	42		T45	1
valid_sources[0x72]	558	1			T76	2		T28	70		T30	1
valid_sources[0x73]	659	1			T45	1		T33	14		T34	9
valid_sources[0x74]	543	1			T76	2		T63	2		T137	1
valid_sources[0x75]	541	1			T32	5		T33	7		T144	2
valid_sources[0x76]	515	1			T5	1		T33	10		T144	12
valid_sources[0x77]	656	1			T5	1		T17	2		T160	2
valid_sources[0x78]	605	1			T15	1		T63	4		T137	1
valid_sources[0x79]	535	1			T32	80		T33	10		T144	2
valid_sources[0x7a]	631	1			T6	1		T33	6		T144	23
valid_sources[0x7b]	528	1			T5	1		T45	1		T33	22
valid_sources[0x7c]	554	1			T82	1		T29	1		T150	1
valid_sources[0x7d]	456	1			T18	3		T33	25		T34	8
valid_sources[0x7e]	492	1			T32	16		T33	4		T34	1
valid_sources[0x7f]	557	1			T5	1		T33	20		T61	1
valid_sources[0x80]	643	1			T15	1		T63	1		T29	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

34778

1

T5

21

T6

14

T15

2

values[0x0]

all_enables

biggest_size

46427

1

T9

1

T5

9

T12

2

values[0x1]

all_enables

biggest_size

44353

1

T5

7

T31

2

T6

3