Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13051270

1

T1

976

T2

1818

T3

83

full_word

51355432

1

T1

44

T2

113

T3

16

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	64406412	1			T1	1020		T2	1931		T3	99
auto[TlIntgErrCmd]	90	1			T108	3		T109	3		T123	5
auto[TlIntgErrData]	101	1			T107	3		T108	3		T109	3
auto[TlIntgErrBoth]	99	1			T107	7		T108	4		T109	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29363761

1

T1

383

T2

841

T3

54

auto[1]

35042941

1

T1

637

T2

1090

T3

45

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6225255	1			T1	381		T2	832		T3	48
auto[TlIntgErrNone]	partial	auto[1]	6825744	1			T1	595		T2	986		T3	35
auto[TlIntgErrNone]	full_word	auto[0]	23138370	1			T1	2		T2	9		T3	6
auto[TlIntgErrNone]	full_word	auto[1]	28217043	1			T1	42		T2	104		T3	10
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T108	1		T123	2		T127	2
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T108	2		T109	3		T123	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T131	1		T132	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T127	1		T128	1		T126	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T107	2		T108	1		T109	2
auto[TlIntgErrData]	partial	auto[1]	45	1			T107	1		T108	2		T109	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T127	1		T124	1		T133	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T123	3		T134	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T107	3		T108	2		T109	3
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T107	4		T108	2		T109	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T131	1		T135	3		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T136	2		-	-		-	-