Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	666046	1			T2	242		T4	39193		T8	639
auto[1]	9886004	1			T1	55		T2	220		T3	24
auto[2]	563752	1			T2	190		T4	34242		T8	411
auto[3]	9792552	1			T1	122		T2	267		T3	15

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13264504	1			T4	2814		T8	1309		T9	2656
auto[1]	2028047	1			T1	7		T2	24		T3	7
auto[2]	2027545	1			T1	8		T2	35		T3	4
auto[3]	3588258	1			T1	162		T2	860		T3	28

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7877194

1

T1

177

T2

914

T3

39

auto[1]

13031160

1

T2

5

T4

135875

T9

6

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	278098	1			T8	530		T5	12		T15	1170
auto[0]	auto[0]	auto[1]	28996	1			T2	2		T8	52		T82	2
auto[0]	auto[0]	auto[2]	28705	1			T2	4		T8	54		T5	2
auto[0]	auto[0]	auto[3]	9299	1			T2	234		T8	3		T82	124
auto[0]	auto[1]	auto[0]	2969451	1			T8	326		T9	1377		T5	12
auto[0]	auto[1]	auto[1]	311510	1			T2	4		T3	3		T8	72
auto[0]	auto[1]	auto[2]	297707	1			T1	2		T2	5		T3	1
auto[0]	auto[1]	auto[3]	65732	1			T1	53		T2	210		T3	20
auto[0]	auto[2]	auto[0]	235971	1			T8	312		T5	9		T15	1042
auto[0]	auto[2]	auto[1]	24428	1			T2	16		T8	31		T5	1
auto[0]	auto[2]	auto[2]	24049	1			T8	62		T5	2		T82	1
auto[0]	auto[2]	auto[3]	7193	1			T2	173		T8	6		T82	96
auto[0]	auto[3]	auto[0]	2927399	1			T8	141		T9	1276		T5	3
auto[0]	auto[3]	auto[1]	293536	1			T1	7		T2	2		T3	4
auto[0]	auto[3]	auto[2]	307377	1			T1	6		T2	26		T3	3
auto[0]	auto[3]	auto[3]	67743	1			T1	109		T2	238		T3	8
auto[1]	auto[0]	auto[0]	10899	1			T4	1307		T28	7		T138	2
auto[1]	auto[0]	auto[1]	47774	1			T4	5793		T144	1		T147	1
auto[1]	auto[0]	auto[2]	47954	1			T4	5889		T58	1		T148	1
auto[1]	auto[0]	auto[3]	214321	1			T2	2		T4	26204		T28	1
auto[1]	auto[1]	auto[0]	3416878	1			T4	213		T9	1		T13	58159
auto[1]	auto[1]	auto[1]	651965	1			T4	6036		T13	5995		T31	3
auto[1]	auto[1]	auto[2]	637103	1			T4	946		T9	1		T13	5858
auto[1]	auto[1]	auto[3]	1535658	1			T2	1		T4	26846		T13	569
auto[1]	auto[2]	auto[0]	8993	1			T4	1183		T5	1		T15	1
auto[1]	auto[2]	auto[1]	40579	1			T4	5366		T28	1		T138	1
auto[1]	auto[2]	auto[2]	40487	1			T4	5006		T144	2		T149	2923
auto[1]	auto[2]	auto[3]	182052	1			T2	1		T4	22687		T149	12879
auto[1]	auto[3]	auto[0]	3416815	1			T4	111		T9	2		T13	58052
auto[1]	auto[3]	auto[1]	629259	1			T4	451		T9	1		T13	5832
auto[1]	auto[3]	auto[2]	644163	1			T4	5063		T9	1		T13	5837
auto[1]	auto[3]	auto[3]	1506260	1			T2	1		T4	22774		T13	607