Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	311694185	104410	0	0
ctrl_regwen_rd_A	311694185	8067	0	0
exec_rd_A	311694185	7391	0	0
exec_regwen_rd_A	311694185	8325	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311694185	104410	0	0
T24	2365	0	0	0
T32	45674	1028	0	0
T33	183068	3099	0	0
T34	0	854	0	0
T48	0	2061	0	0
T49	0	3018	0	0
T50	0	4353	0	0
T51	0	758	0	0
T52	0	1131	0	0
T53	0	1017	0	0
T54	0	3714	0	0
T55	434889	0	0	0
T56	8692	0	0	0
T57	103456	0	0	0
T58	236451	0	0	0
T59	76030	0	0	0
T60	61151	0	0	0
T61	189352	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311694185	8067	0	0
T21	21100	0	0	0
T34	79552	183	0	0
T49	0	819	0	0
T51	0	213	0	0
T52	0	283	0	0
T53	0	291	0	0
T110	0	204	0	0
T111	0	207	0	0
T112	0	924	0	0
T113	0	175	0	0
T114	0	54	0	0
T115	299070	0	0	0
T116	283358	0	0	0
T117	12874	0	0	0
T118	103267	0	0	0
T119	7047	0	0	0
T120	63768	0	0	0
T121	13396	0	0	0
T122	3650	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311694185	7391	0	0
T21	21100	0	0	0
T34	79552	150	0	0
T49	0	634	0	0
T51	0	259	0	0
T52	0	231	0	0
T53	0	180	0	0
T110	0	252	0	0
T111	0	196	0	0
T112	0	804	0	0
T113	0	173	0	0
T114	0	89	0	0
T115	299070	0	0	0
T116	283358	0	0	0
T117	12874	0	0	0
T118	103267	0	0	0
T119	7047	0	0	0
T120	63768	0	0	0
T121	13396	0	0	0
T122	3650	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311694185	8325	0	0
T21	21100	0	0	0
T34	79552	136	0	0
T49	0	869	0	0
T51	0	312	0	0
T52	0	262	0	0
T53	0	238	0	0
T110	0	276	0	0
T111	0	159	0	0
T112	0	816	0	0
T113	0	90	0	0
T114	0	97	0	0
T115	299070	0	0	0
T116	283358	0	0	0
T117	12874	0	0	0
T118	103267	0	0	0
T119	7047	0	0	0
T120	63768	0	0	0
T121	13396	0	0	0
T122	3650	0	0	0