Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13843018	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59322297

1

T1

7445

T2

261

T3

397

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36480327	1			T1	4460		T2	145		T3	232
values[0x0]	16960174	1			T1	2086		T2	59		T3	102
values[0x1]	19724814	1			T1	2504		T2	75		T3	130

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6896611	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66268704

1

T1

8263

T2

273

T3

426

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	347689	1			T1	36		T6	593		T12	483
valid_sources[0x01]	324194	1			T1	34		T3	2		T6	603
valid_sources[0x02]	269886	1			T1	44		T3	2		T6	632
valid_sources[0x03]	273295	1			T1	52		T3	1		T6	619
valid_sources[0x04]	265551	1			T1	28		T6	558		T12	476
valid_sources[0x05]	286279	1			T1	31		T3	2		T6	573
valid_sources[0x06]	243791	1			T1	39		T3	1		T6	601
valid_sources[0x07]	278175	1			T1	40		T6	640		T12	453
valid_sources[0x08]	304120	1			T1	37		T6	552		T12	455
valid_sources[0x09]	263676	1			T1	22		T3	1		T6	633
valid_sources[0x0a]	283235	1			T1	51		T5	13569		T6	629
valid_sources[0x0b]	302845	1			T1	53		T6	602		T12	475
valid_sources[0x0c]	255674	1			T1	36		T3	5		T5	4392
valid_sources[0x0d]	305825	1			T1	46		T3	3		T5	18893
valid_sources[0x0e]	284608	1			T1	31		T3	2		T6	682
valid_sources[0x0f]	243036	1			T1	34		T6	567		T12	453
valid_sources[0x10]	331297	1			T1	34		T6	605		T12	468
valid_sources[0x11]	254931	1			T1	42		T3	5		T6	578
valid_sources[0x12]	313626	1			T1	39		T3	2		T6	585
valid_sources[0x13]	254174	1			T1	45		T3	1		T5	63
valid_sources[0x14]	281607	1			T1	30		T3	2		T6	552
valid_sources[0x15]	289209	1			T1	37		T3	2		T6	613
valid_sources[0x16]	312863	1			T1	38		T3	11		T6	612
valid_sources[0x17]	336932	1			T1	27		T6	571		T12	481
valid_sources[0x18]	298858	1			T1	35		T5	37		T6	576
valid_sources[0x19]	279938	1			T1	44		T6	575		T12	478
valid_sources[0x1a]	303209	1			T1	28		T3	4		T6	606
valid_sources[0x1b]	266515	1			T1	38		T3	12		T6	570
valid_sources[0x1c]	267258	1			T1	35		T3	6		T6	618
valid_sources[0x1d]	299813	1			T1	32		T6	632		T12	424
valid_sources[0x1e]	257906	1			T1	30		T3	1		T6	617
valid_sources[0x1f]	249119	1			T1	38		T3	6		T6	625
valid_sources[0x20]	272748	1			T1	44		T3	2		T6	633
valid_sources[0x21]	250901	1			T1	31		T3	1		T6	609
valid_sources[0x22]	297248	1			T1	28		T6	590		T12	422
valid_sources[0x23]	270481	1			T1	38		T3	9		T6	577
valid_sources[0x24]	266906	1			T1	51		T3	2		T4	3071
valid_sources[0x25]	348071	1			T1	35		T6	578		T12	444
valid_sources[0x26]	289781	1			T1	34		T3	1		T6	613
valid_sources[0x27]	276813	1			T1	28		T3	1		T5	2705
valid_sources[0x28]	251639	1			T1	31		T3	2		T6	584
valid_sources[0x29]	252114	1			T1	26		T3	2		T6	597
valid_sources[0x2a]	271024	1			T1	24		T3	7		T5	119
valid_sources[0x2b]	251340	1			T1	29		T3	1		T6	563
valid_sources[0x2c]	301767	1			T1	45		T5	634		T6	605
valid_sources[0x2d]	342442	1			T1	35		T6	619		T12	462
valid_sources[0x2e]	330827	1			T1	26		T3	2		T6	611
valid_sources[0x2f]	265800	1			T1	35		T6	603		T12	430
valid_sources[0x30]	292936	1			T1	32		T3	1		T6	605
valid_sources[0x31]	321772	1			T1	28		T3	3		T6	598
valid_sources[0x32]	331664	1			T1	28		T6	630		T12	484
valid_sources[0x33]	265615	1			T1	36		T6	585		T12	474
valid_sources[0x34]	248105	1			T1	42		T6	615		T12	445
valid_sources[0x35]	288109	1			T1	39		T6	595		T12	443
valid_sources[0x36]	315728	1			T1	30		T5	5582		T6	611
valid_sources[0x37]	265657	1			T1	44		T3	5		T5	13296
valid_sources[0x38]	306423	1			T1	53		T6	593		T12	440
valid_sources[0x39]	412950	1			T1	30		T6	572		T12	481
valid_sources[0x3a]	257465	1			T1	33		T6	631		T12	441
valid_sources[0x3b]	298964	1			T1	27		T6	624		T12	485
valid_sources[0x3c]	384392	1			T1	25		T5	4110		T6	636
valid_sources[0x3d]	273257	1			T1	23		T6	673		T12	458
valid_sources[0x3e]	259354	1			T1	37		T3	2		T5	1934
valid_sources[0x3f]	280007	1			T1	31		T3	4		T6	620
valid_sources[0x40]	369388	1			T1	43		T2	23		T3	1
valid_sources[0x41]	321300	1			T1	31		T3	3		T6	587
valid_sources[0x42]	269974	1			T1	42		T3	2		T5	237
valid_sources[0x43]	278341	1			T1	30		T3	1		T6	590
valid_sources[0x44]	260942	1			T1	36		T3	2		T6	601
valid_sources[0x45]	305639	1			T1	25		T3	2		T6	577
valid_sources[0x46]	282308	1			T1	29		T6	628		T12	454
valid_sources[0x47]	260405	1			T1	29		T3	1		T5	86
valid_sources[0x48]	277043	1			T1	37		T3	2		T6	582
valid_sources[0x49]	268669	1			T1	42		T6	604		T12	458
valid_sources[0x4a]	293054	1			T1	26		T6	597		T12	445
valid_sources[0x4b]	255005	1			T1	34		T3	5		T5	19
valid_sources[0x4c]	333770	1			T1	41		T3	5		T6	599
valid_sources[0x4d]	278221	1			T1	56		T3	4		T6	622
valid_sources[0x4e]	281838	1			T1	36		T3	1		T5	1692
valid_sources[0x4f]	268916	1			T1	41		T6	626		T12	466
valid_sources[0x50]	286309	1			T1	34		T3	1		T5	9785
valid_sources[0x51]	257867	1			T1	25		T3	7		T6	625
valid_sources[0x52]	245763	1			T1	44		T3	3		T6	607
valid_sources[0x53]	284803	1			T1	34		T3	7		T6	566
valid_sources[0x54]	297826	1			T1	49		T3	1		T6	624
valid_sources[0x55]	261175	1			T1	25		T3	7		T6	605
valid_sources[0x56]	279500	1			T1	21		T3	4		T6	603
valid_sources[0x57]	276782	1			T1	36		T2	140		T3	3
valid_sources[0x58]	296930	1			T1	34		T5	3		T6	605
valid_sources[0x59]	269176	1			T1	44		T3	5		T5	31
valid_sources[0x5a]	265918	1			T1	30		T3	10		T6	635
valid_sources[0x5b]	263788	1			T1	34		T3	1		T6	603
valid_sources[0x5c]	352324	1			T1	22		T3	3		T6	571
valid_sources[0x5d]	296313	1			T1	26		T3	1		T5	3323
valid_sources[0x5e]	263776	1			T1	40		T3	2		T6	573
valid_sources[0x5f]	290835	1			T1	33		T3	3		T5	48
valid_sources[0x60]	256464	1			T1	35		T5	965		T6	587
valid_sources[0x61]	303568	1			T1	33		T3	2		T6	570
valid_sources[0x62]	314338	1			T1	35		T3	2		T6	549
valid_sources[0x63]	276337	1			T1	39		T3	5		T6	543
valid_sources[0x64]	252199	1			T1	30		T3	1		T6	597
valid_sources[0x65]	289012	1			T1	40		T3	5		T6	543
valid_sources[0x66]	283465	1			T1	39		T6	664		T12	411
valid_sources[0x67]	343253	1			T1	33		T3	1		T6	572
valid_sources[0x68]	288054	1			T1	29		T6	658		T12	502
valid_sources[0x69]	290454	1			T1	44		T6	559		T12	476
valid_sources[0x6a]	264641	1			T1	57		T6	631		T12	423
valid_sources[0x6b]	285621	1			T1	35		T3	1		T5	1008
valid_sources[0x6c]	326222	1			T1	45		T3	5		T6	591
valid_sources[0x6d]	273358	1			T1	47		T3	2		T5	56
valid_sources[0x6e]	256019	1			T1	42		T3	1		T6	629
valid_sources[0x6f]	268459	1			T1	34		T6	607		T12	408
valid_sources[0x70]	275760	1			T1	50		T3	12		T6	585
valid_sources[0x71]	258681	1			T1	37		T3	1		T5	10727
valid_sources[0x72]	251188	1			T1	47		T6	608		T12	481
valid_sources[0x73]	283954	1			T1	46		T5	5216		T6	515
valid_sources[0x74]	282785	1			T1	59		T3	4		T5	2077
valid_sources[0x75]	285000	1			T1	27		T3	1		T6	588
valid_sources[0x76]	288251	1			T1	33		T6	604		T12	470
valid_sources[0x77]	276645	1			T1	28		T3	6		T6	643
valid_sources[0x78]	262252	1			T1	44		T3	3		T6	597
valid_sources[0x79]	289014	1			T1	33		T6	587		T12	451
valid_sources[0x7a]	294837	1			T1	37		T5	19		T6	604
valid_sources[0x7b]	398562	1			T1	30		T3	5		T6	605
valid_sources[0x7c]	259189	1			T1	37		T3	1		T6	583
valid_sources[0x7d]	285744	1			T1	28		T3	1		T6	573
valid_sources[0x7e]	267351	1			T1	16		T6	576		T12	489
valid_sources[0x7f]	366528	1			T1	47		T5	10064		T6	580
valid_sources[0x80]	244118	1			T1	27		T6	581		T12	437

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29559630

1

T1

3661

T2

134

T3

198

values[0x0]

all_enables

biggest_size

14882084

1

T1

1851

T2

57

T3

92

values[0x1]

all_enables

biggest_size

14880583

1

T1

1933

T2

70

T3

107

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33661	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

132323

1

T3

1

T5

7

T6

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	48430	1			T17	9		T14	27		T7	37
values[0x0]	56612	1			T1	1		T2	1		T5	25
values[0x1]	60942	1			T1	1		T2	1		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25857	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

140127

1

T3

2

T5

11

T10

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	653	1			T6	2		T17	4		T28	4
valid_sources[0x01]	482	1			T14	2		T25	2		T29	4
valid_sources[0x02]	714	1			T142	1		T59	3		T29	10
valid_sources[0x03]	576	1			T5	6		T9	64		T26	2
valid_sources[0x04]	525	1			T5	1		T14	2		T61	1
valid_sources[0x05]	681	1			T43	4		T26	1		T60	2
valid_sources[0x06]	450	1			T44	1		T25	1		T59	1
valid_sources[0x07]	556	1			T17	2		T14	1		T8	2
valid_sources[0x08]	682	1			T28	189		T29	2		T117	14
valid_sources[0x09]	866	1			T14	2		T8	1		T29	4
valid_sources[0x0a]	654	1			T28	1		T29	2		T138	4
valid_sources[0x0b]	512	1			T14	1		T25	1		T59	2
valid_sources[0x0c]	565	1			T14	1		T65	2		T29	6
valid_sources[0x0d]	642	1			T14	1		T15	1		T28	83
valid_sources[0x0e]	823	1			T14	1		T15	1		T52	1
valid_sources[0x0f]	476	1			T14	2		T15	1		T25	1
valid_sources[0x10]	518	1			T11	1		T14	2		T28	1
valid_sources[0x11]	586	1			T14	1		T43	1		T59	1
valid_sources[0x12]	496	1			T14	1		T8	1		T29	6
valid_sources[0x13]	613	1			T14	3		T25	1		T57	1
valid_sources[0x14]	1091	1			T28	1		T60	2		T29	3
valid_sources[0x15]	438	1			T17	9		T8	1		T142	1
valid_sources[0x16]	479	1			T14	1		T8	1		T60	6
valid_sources[0x17]	524	1			T5	3		T14	2		T8	1
valid_sources[0x18]	504	1			T14	2		T8	1		T28	14
valid_sources[0x19]	586	1			T14	3		T15	1		T59	1
valid_sources[0x1a]	415	1			T14	1		T8	2		T54	1
valid_sources[0x1b]	583	1			T25	1		T59	1		T26	1
valid_sources[0x1c]	893	1			T8	1		T60	1		T29	1
valid_sources[0x1d]	462	1			T14	1		T28	1		T57	2
valid_sources[0x1e]	811	1			T14	1		T8	1		T28	114
valid_sources[0x1f]	536	1			T2	1		T14	1		T29	8
valid_sources[0x20]	477	1			T14	1		T62	1		T8	1
valid_sources[0x21]	807	1			T14	2		T15	1		T8	1
valid_sources[0x22]	706	1			T14	4		T8	2		T25	1
valid_sources[0x23]	1101	1			T17	5		T14	1		T8	2
valid_sources[0x24]	618	1			T16	1		T14	1		T8	2
valid_sources[0x25]	833	1			T6	1		T14	1		T52	1
valid_sources[0x26]	933	1			T3	2		T5	4		T17	6
valid_sources[0x27]	611	1			T6	1		T17	2		T14	1
valid_sources[0x28]	754	1			T14	2		T28	82		T59	1
valid_sources[0x29]	581	1			T8	1		T28	66		T52	1
valid_sources[0x2a]	636	1			T6	1		T12	1		T17	3
valid_sources[0x2b]	733	1			T62	1		T8	1		T60	1
valid_sources[0x2c]	546	1			T14	2		T25	2		T26	1
valid_sources[0x2d]	464	1			T5	2		T6	1		T14	3
valid_sources[0x2e]	575	1			T14	1		T8	1		T28	5
valid_sources[0x2f]	661	1			T26	1		T60	1		T101	5
valid_sources[0x30]	511	1			T14	1		T26	2		T99	1
valid_sources[0x31]	805	1			T8	1		T28	96		T60	1
valid_sources[0x32]	585	1			T29	3		T143	1		T30	6
valid_sources[0x33]	601	1			T14	1		T43	3		T26	3
valid_sources[0x34]	616	1			T44	1		T59	1		T60	4
valid_sources[0x35]	557	1			T6	1		T14	1		T52	2
valid_sources[0x36]	838	1			T14	2		T28	1		T57	1
valid_sources[0x37]	701	1			T14	1		T21	1		T28	5
valid_sources[0x38]	730	1			T13	1		T14	2		T28	1
valid_sources[0x39]	687	1			T10	4		T14	2		T25	1
valid_sources[0x3a]	651	1			T16	1		T142	2		T28	4
valid_sources[0x3b]	1032	1			T8	1		T28	1		T60	3
valid_sources[0x3c]	730	1			T16	1		T14	2		T28	1
valid_sources[0x3d]	851	1			T14	1		T28	126		T54	1
valid_sources[0x3e]	544	1			T28	84		T52	1		T25	1
valid_sources[0x3f]	751	1			T14	1		T28	1		T25	1
valid_sources[0x40]	712	1			T8	1		T59	1		T26	1
valid_sources[0x41]	451	1			T59	3		T60	1		T29	3
valid_sources[0x42]	682	1			T28	3		T26	1		T29	8
valid_sources[0x43]	514	1			T14	1		T8	1		T59	2
valid_sources[0x44]	560	1			T59	2		T60	1		T29	2
valid_sources[0x45]	666	1			T16	1		T14	1		T8	1
valid_sources[0x46]	526	1			T28	99		T29	5		T135	3
valid_sources[0x47]	652	1			T14	2		T8	2		T26	1
valid_sources[0x48]	532	1			T1	1		T14	1		T26	1
valid_sources[0x49]	461	1			T2	1		T59	1		T26	1
valid_sources[0x4a]	533	1			T13	1		T62	1		T28	7
valid_sources[0x4b]	856	1			T28	1		T59	1		T29	3
valid_sources[0x4c]	697	1			T14	1		T8	1		T26	2
valid_sources[0x4d]	978	1			T16	1		T14	3		T59	2
valid_sources[0x4e]	747	1			T28	6		T23	1		T29	5
valid_sources[0x4f]	769	1			T14	1		T21	1		T28	2
valid_sources[0x50]	605	1			T16	3		T14	2		T28	1
valid_sources[0x51]	632	1			T5	4		T14	2		T8	2
valid_sources[0x52]	585	1			T52	2		T26	1		T29	7
valid_sources[0x53]	499	1			T5	1		T14	2		T62	1
valid_sources[0x54]	537	1			T14	2		T28	3		T59	1
valid_sources[0x55]	538	1			T14	1		T62	1		T21	1
valid_sources[0x56]	470	1			T29	7		T24	1		T30	10
valid_sources[0x57]	510	1			T5	1		T14	1		T8	1
valid_sources[0x58]	886	1			T52	1		T25	1		T29	6
valid_sources[0x59]	934	1			T54	1		T144	1		T29	6
valid_sources[0x5a]	1153	1			T8	1		T59	3		T60	3
valid_sources[0x5b]	773	1			T6	1		T14	1		T8	1
valid_sources[0x5c]	895	1			T16	3		T142	1		T28	82
valid_sources[0x5d]	552	1			T14	1		T7	2		T28	1
valid_sources[0x5e]	580	1			T8	1		T25	1		T59	1
valid_sources[0x5f]	556	1			T59	1		T26	1		T29	2
valid_sources[0x60]	483	1			T5	2		T14	1		T62	1
valid_sources[0x61]	636	1			T14	1		T26	1		T60	1
valid_sources[0x62]	824	1			T14	1		T25	1		T59	1
valid_sources[0x63]	568	1			T14	1		T28	1		T29	5
valid_sources[0x64]	505	1			T14	1		T8	1		T26	2
valid_sources[0x65]	593	1			T5	1		T8	1		T26	1
valid_sources[0x66]	546	1			T14	1		T25	2		T59	2
valid_sources[0x67]	537	1			T14	1		T28	2		T26	2
valid_sources[0x68]	784	1			T8	1		T25	1		T26	1
valid_sources[0x69]	554	1			T14	1		T8	1		T21	1
valid_sources[0x6a]	566	1			T16	1		T14	2		T8	1
valid_sources[0x6b]	611	1			T6	1		T52	1		T26	1
valid_sources[0x6c]	482	1			T14	1		T8	1		T99	1
valid_sources[0x6d]	683	1			T28	2		T25	2		T29	6
valid_sources[0x6e]	402	1			T5	2		T14	2		T62	1
valid_sources[0x6f]	805	1			T14	2		T28	86		T136	1
valid_sources[0x70]	841	1			T14	2		T25	1		T26	1
valid_sources[0x71]	393	1			T29	1		T145	1		T136	4
valid_sources[0x72]	855	1			T17	3		T14	2		T142	1
valid_sources[0x73]	698	1			T14	1		T146	1		T29	3
valid_sources[0x74]	497	1			T14	1		T28	3		T54	1
valid_sources[0x75]	831	1			T8	1		T28	227		T53	1
valid_sources[0x76]	592	1			T59	1		T29	7		T24	1
valid_sources[0x77]	775	1			T14	1		T8	2		T29	1
valid_sources[0x78]	535	1			T26	1		T29	4		T24	1
valid_sources[0x79]	563	1			T14	2		T8	1		T28	2
valid_sources[0x7a]	595	1			T142	2		T44	1		T29	2
valid_sources[0x7b]	474	1			T14	2		T15	1		T84	1
valid_sources[0x7c]	532	1			T14	2		T8	1		T28	2
valid_sources[0x7d]	664	1			T16	1		T21	1		T28	2
valid_sources[0x7e]	496	1			T15	2		T8	1		T59	2
valid_sources[0x7f]	567	1			T6	1		T14	2		T8	2
valid_sources[0x80]	527	1			T28	27		T25	1		T59	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

36362

1

T17

5

T14

10

T7

15

values[0x0]

all_enables

biggest_size

48566

1

T5

3

T6

3

T13

2

values[0x1]

all_enables

biggest_size

47395

1

T3

1

T5

4

T6

4