Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13501242

1

T1

1605

T2

18

T3

67

full_word

54183132

1

T1

7445

T2

261

T3

397

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	67684074	1			T1	9050		T2	279		T3	464
auto[TlIntgErrCmd]	90	1			T107	5		T108	3		T109	5
auto[TlIntgErrData]	102	1			T107	2		T108	3		T109	5
auto[TlIntgErrBoth]	108	1			T107	3		T108	4		T109	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30956643

1

T1

4460

T2

145

T3

232

auto[1]

36727731

1

T1

4590

T2

134

T3

232

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6450168	1			T1	799		T2	11		T3	34
auto[TlIntgErrNone]	partial	auto[1]	7050808	1			T1	806		T2	7		T3	33
auto[TlIntgErrNone]	full_word	auto[0]	24506350	1			T1	3661		T2	134		T3	198
auto[TlIntgErrNone]	full_word	auto[1]	29676748	1			T1	3784		T2	127		T3	199
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T107	2		T108	3		T109	1
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T107	3		T109	3		T123	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T123	1		T124	1		T129	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T109	1		T130	1		T124	1
auto[TlIntgErrData]	partial	auto[0]	32	1			T107	1		T109	1		T123	2
auto[TlIntgErrData]	partial	auto[1]	56	1			T108	2		T109	4		T123	8
auto[TlIntgErrData]	full_word	auto[0]	3	1			T124	1		T122	1		T127	1
auto[TlIntgErrData]	full_word	auto[1]	11	1			T107	1		T108	1		T124	3
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T107	2		T108	3		T109	3
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T107	1		T108	1		T109	5
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T109	1		T123	1		T125	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T109	1		T128	1		T131	1