Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	767325	1			T14	23553		T7	34		T15	7116
auto[1]	10721040	1			T1	4460		T2	143		T3	231
auto[2]	638581	1			T14	21052		T7	29		T15	4533
auto[3]	10598530	1			T1	4589		T2	129		T3	231

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14373321	1			T1	6095		T2	251		T3	351
auto[1]	2208016	1			T1	1349		T2	6		T3	44
auto[2]	2202991	1			T1	1317		T2	15		T3	58
auto[3]	3941148	1			T1	288		T3	9		T5	818

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7870651

1

T1

9039

T2

272

T3

462

auto[1]

14854825

1

T1

10

T5

102

T6

94

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	281919	1			T14	19483		T7	23		T15	5877
auto[0]	auto[0]	auto[1]	28753	1			T14	1940		T7	5		T15	600
auto[0]	auto[0]	auto[2]	28844	1			T14	1907		T7	6		T15	574
auto[0]	auto[0]	auto[3]	7939	1			T14	203		T15	55		T61	89
auto[0]	auto[1]	auto[0]	2963189	1			T1	2957		T2	131		T3	183
auto[0]	auto[1]	auto[1]	315448	1			T1	703		T2	1		T3	14
auto[0]	auto[1]	auto[2]	295323	1			T1	670		T2	11		T3	28
auto[0]	auto[1]	auto[3]	65932	1			T1	129		T3	6		T5	429
auto[0]	auto[2]	auto[0]	237621	1			T14	17506		T7	23		T15	3514
auto[0]	auto[2]	auto[1]	24569	1			T14	1751		T7	2		T15	335
auto[0]	auto[2]	auto[2]	23430	1			T14	1620		T7	3		T15	615
auto[0]	auto[2]	auto[3]	6079	1			T14	156		T7	1		T15	68
auto[0]	auto[3]	auto[0]	2918879	1			T1	3132		T2	120		T3	168
auto[0]	auto[3]	auto[1]	291683	1			T1	645		T2	5		T3	30
auto[0]	auto[3]	auto[2]	311936	1			T1	644		T2	4		T3	30
auto[0]	auto[3]	auto[3]	69107	1			T1	159		T3	3		T5	388
auto[1]	auto[0]	auto[0]	14051	1			T14	17		T15	9		T64	9
auto[1]	auto[0]	auto[1]	62240	1			T14	3		T64	1		T8	4
auto[1]	auto[0]	auto[2]	62204	1			T64	1		T138	1		T103	3196
auto[1]	auto[0]	auto[3]	281375	1			T15	1		T61	2		T137	4
auto[1]	auto[1]	auto[0]	3974285	1			T1	1		T5	42		T6	35
auto[1]	auto[1]	auto[1]	732325	1			T5	1		T6	1		T12	1114
auto[1]	auto[1]	auto[2]	708876	1			T5	5		T6	6		T12	386
auto[1]	auto[1]	auto[3]	1665662	1			T12	5153		T53	886		T83	1
auto[1]	auto[2]	auto[0]	12165	1			T14	11		T15	1		T64	6
auto[1]	auto[2]	auto[1]	54183	1			T14	5		T64	3		T8	2
auto[1]	auto[2]	auto[2]	50714	1			T14	3		T64	1		T8	2
auto[1]	auto[2]	auto[3]	229820	1			T139	1		T103	12071		T140	5575
auto[1]	auto[3]	auto[0]	3971212	1			T1	5		T5	41		T6	43
auto[1]	auto[3]	auto[1]	698815	1			T1	1		T5	6		T6	5
auto[1]	auto[3]	auto[2]	721664	1			T1	3		T5	6		T6	3
auto[1]	auto[3]	auto[3]	1615234	1			T5	1		T6	1		T12	5053