Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	153774176	1			T1	286616		T2	1924		T3	55770
instr_valid_dis	122342970	1			T1	286616		T2	1924		T3	55770
instr_en	22172930	1			T8	178402		T5	342214		T10	172178

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10913573	1			T8	20134		T5	92708		T10	89636
sram_ifetch_valid_disable	119622351	1			T1	286616		T2	1924		T3	55770
sram_ifetch_enable	23238252	1			T8	53456		T5	207850		T10	143972

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	153774176	1			T1	286616		T2	1924		T3	55770
hw_debug_en_valid_off	119784344	1			T1	286616		T2	1924		T3	55770
hw_debug_en_on	23015246	1			T8	56474		T5	251374		T10	198584

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	119622351	1			T1	286616		T2	1924		T3	55770
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	107504069	1			T1	286616		T2	1924		T3	55770
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8520988	1			T8	105322		T5	187172		T10	82946
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4144718	1			T5	15614		T10	54912		T12	57392
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1700711	1			T5	466		T10	54912		T22	29034
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1497633	1			T5	15148		T22	68345		T6	16536
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4402639	1			T8	5782		T5	64456		T10	17782
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2160892	1			T10	17782		T12	10910		T22	40590
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1685255	1			T8	5782		T5	23926		T23	52808
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9966200	1			T8	17642		T5	108978		T10	100120
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	5024958	1			T10	35486		T12	255140		T41	18470
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3518236	1			T8	17642		T5	108978		T10	64634

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9645529	1			T8	52946		T5	103330		T10	89232
lc_exec_en	8646407	1			T8	33050		T5	77940		T10	80682
valid_exec_dis	114936106	1			T1	286616		T2	1924		T3	55770
invalid_exec_dis	34151825	1			T8	73590		T5	300558		T10	233608