Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.08 99.81 96.99 100.00 100.00 98.57 99.70 98.52


Total tests in report: 1035
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
86.76 86.76 97.66 97.66 81.56 81.56 95.03 95.03 71.43 71.43 89.63 89.63 95.05 95.05 76.99 76.99 /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3670279619
94.62 7.86 99.12 1.46 88.18 6.62 98.03 3.00 100.00 28.57 95.97 6.34 95.35 0.30 85.71 8.72 /workspace/coverage/default/14.sram_ctrl_stress_all.731509204
95.70 1.08 99.32 0.19 89.09 0.91 98.25 0.21 100.00 0.00 96.83 0.86 95.35 0.00 91.09 5.38 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2921887507
96.71 1.01 99.51 0.19 91.69 2.60 98.43 0.18 100.00 0.00 97.98 1.15 96.25 0.90 93.14 2.04 /workspace/coverage/default/10.sram_ctrl_stress_all.1156378025
97.46 0.75 99.71 0.19 93.64 1.95 99.14 0.72 100.00 0.00 98.85 0.86 96.85 0.60 94.06 0.93 /workspace/coverage/default/3.sram_ctrl_sec_cm.1500757361
97.78 0.31 99.71 0.00 93.64 0.00 99.14 0.00 100.00 0.00 98.85 0.00 97.00 0.15 96.10 2.04 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.3346053452
97.98 0.20 99.71 0.00 93.77 0.13 99.14 0.00 100.00 0.00 98.85 0.00 97.90 0.90 96.47 0.37 /workspace/coverage/default/18.sram_ctrl_access_during_key_req.908471385
98.17 0.19 99.71 0.00 93.77 0.00 99.14 0.00 100.00 0.00 98.85 0.00 99.25 1.35 96.47 0.00 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3820692769
98.30 0.13 99.71 0.00 93.77 0.00 99.14 0.00 100.00 0.00 98.85 0.00 99.25 0.00 97.40 0.93 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3383573764
98.42 0.12 99.81 0.10 93.77 0.00 99.86 0.72 100.00 0.00 98.85 0.00 99.25 0.00 97.40 0.00 /workspace/coverage/default/14.sram_ctrl_ram_cfg.2095785585
98.52 0.11 99.81 0.00 93.77 0.00 99.86 0.00 100.00 0.00 98.85 0.00 99.25 0.00 98.14 0.74 /workspace/coverage/default/46.sram_ctrl_stress_all.1637726608
98.59 0.07 99.81 0.00 94.16 0.39 99.93 0.07 100.00 0.00 98.85 0.00 99.25 0.00 98.14 0.00 /workspace/coverage/default/10.sram_ctrl_alert_test.1268994985
98.64 0.05 99.81 0.00 94.16 0.00 100.00 0.07 100.00 0.00 98.85 0.00 99.55 0.30 98.14 0.00 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1426781705
98.67 0.03 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.55 0.00 98.33 0.19 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2901076044
98.70 0.03 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.55 0.00 98.52 0.19 /workspace/coverage/default/11.sram_ctrl_regwen.1682827334
98.72 0.02 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.70 0.15 98.52 0.00 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3910936849

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1423094899
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.700411455
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.37809298
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1621906134
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1036414350
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.851442054
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3905088641
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.101374460
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.132123064
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.275314722
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3472654933
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2905806310
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2344501650
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.501021885
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1144427298
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.536930434
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.4208359247
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1871297733
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2754900592
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2374727751
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2562483885
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1688335948
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2688273337
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3664182155
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2192304470
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1046505949
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3877225172
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2794945595
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.777905115
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1225415401
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1272480839
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2697270716
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1754524277
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3131176242
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3064675063
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.344561358
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3753506395
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3969978320
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.324967074
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1644957551
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3710208552
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.147168519
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3084526248
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.4019509093
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.398337032
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3015687551
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1631971337
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1895020895
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3472112309
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3458715424
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1763189869
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2616774218
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3980438031
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3985946705
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.4248936641
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3324880911
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2956449788
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2329404333
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1359888064
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1785514039
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1100710761
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1685374252
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1333793163
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.327651862
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1486536754
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.896286341
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3702025456
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1537735855
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1241735924
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2592943290
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3814539530
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2536460102
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.382711871
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4147966384
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.779657020
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1060869105
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1010294832
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.255481641
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3696760734
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3671867779
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.322408751
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2025590460
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3807216633
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.89542365
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3157231919
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.618950596
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2056487892
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2762137423
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2727710194
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3302753997
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3126807763
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.4032481936
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3046535457
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3722154939
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.246051094
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3769664597
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3408368704
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3208189440
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3143341483
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3573306021
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2314661890
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.4105870392
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3337607445
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2187544
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1872847953
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.275757497
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2927731593
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1296059997
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3412775292
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.347460523
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.496910528
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3261639227
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.122246904
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2468197597
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.690474797
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1164740477
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2774247888
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1442363718
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.962844652
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3219265337
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3060413775
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1206140512
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1567188566
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1807963499
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1538677143
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1233835453
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4143680091
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1452946423
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1573549432
/workspace/coverage/default/0.sram_ctrl_alert_test.968028949
/workspace/coverage/default/0.sram_ctrl_bijection.1238383927
/workspace/coverage/default/0.sram_ctrl_executable.490894802
/workspace/coverage/default/0.sram_ctrl_lc_escalation.4082431337
/workspace/coverage/default/0.sram_ctrl_max_throughput.3571353906
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.573700407
/workspace/coverage/default/0.sram_ctrl_mem_walk.2001840758
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3035399894
/workspace/coverage/default/0.sram_ctrl_partial_access.276136638
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.308983064
/workspace/coverage/default/0.sram_ctrl_ram_cfg.1163262823
/workspace/coverage/default/0.sram_ctrl_regwen.3578077975
/workspace/coverage/default/0.sram_ctrl_sec_cm.3048610442
/workspace/coverage/default/0.sram_ctrl_smoke.2214161236
/workspace/coverage/default/0.sram_ctrl_stress_all.247996006
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3114885601
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.1828307361
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2753542353
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2685105758
/workspace/coverage/default/1.sram_ctrl_alert_test.1644519316
/workspace/coverage/default/1.sram_ctrl_bijection.1522027648
/workspace/coverage/default/1.sram_ctrl_executable.2715911096
/workspace/coverage/default/1.sram_ctrl_lc_escalation.2782901352
/workspace/coverage/default/1.sram_ctrl_max_throughput.2867383223
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.2388353146
/workspace/coverage/default/1.sram_ctrl_mem_walk.3777065540
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2611386046
/workspace/coverage/default/1.sram_ctrl_partial_access.2095376014
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3197285034
/workspace/coverage/default/1.sram_ctrl_ram_cfg.587833065
/workspace/coverage/default/1.sram_ctrl_regwen.3937680721
/workspace/coverage/default/1.sram_ctrl_sec_cm.3215606464
/workspace/coverage/default/1.sram_ctrl_smoke.2246684252
/workspace/coverage/default/1.sram_ctrl_stress_all.1743786508
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.45282382
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2124998682
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3864293512
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.4192752942
/workspace/coverage/default/10.sram_ctrl_bijection.1390908533
/workspace/coverage/default/10.sram_ctrl_executable.101313988
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3433093462
/workspace/coverage/default/10.sram_ctrl_max_throughput.522554552
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.4191650021
/workspace/coverage/default/10.sram_ctrl_mem_walk.2623258437
/workspace/coverage/default/10.sram_ctrl_multiple_keys.827165120
/workspace/coverage/default/10.sram_ctrl_partial_access.1425924922
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2273637999
/workspace/coverage/default/10.sram_ctrl_ram_cfg.19552701
/workspace/coverage/default/10.sram_ctrl_regwen.305850260
/workspace/coverage/default/10.sram_ctrl_smoke.326699350
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.850509879
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.857586825
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2298822370
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.165428315
/workspace/coverage/default/11.sram_ctrl_alert_test.1861508943
/workspace/coverage/default/11.sram_ctrl_bijection.2923911054
/workspace/coverage/default/11.sram_ctrl_executable.2166350596
/workspace/coverage/default/11.sram_ctrl_lc_escalation.2833657675
/workspace/coverage/default/11.sram_ctrl_max_throughput.3748655229
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.1049424301
/workspace/coverage/default/11.sram_ctrl_mem_walk.3624201165
/workspace/coverage/default/11.sram_ctrl_multiple_keys.2818953880
/workspace/coverage/default/11.sram_ctrl_partial_access.2641057725
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3700463275
/workspace/coverage/default/11.sram_ctrl_ram_cfg.4223548767
/workspace/coverage/default/11.sram_ctrl_smoke.3420028971
/workspace/coverage/default/11.sram_ctrl_stress_all.1286742942
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.160510464
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2845619137
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.708251826
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.3651114103
/workspace/coverage/default/12.sram_ctrl_alert_test.3647796564
/workspace/coverage/default/12.sram_ctrl_bijection.938082185
/workspace/coverage/default/12.sram_ctrl_executable.2006559
/workspace/coverage/default/12.sram_ctrl_lc_escalation.3345195908
/workspace/coverage/default/12.sram_ctrl_max_throughput.2667404655
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.3848403631
/workspace/coverage/default/12.sram_ctrl_mem_walk.3299610187
/workspace/coverage/default/12.sram_ctrl_multiple_keys.1911287446
/workspace/coverage/default/12.sram_ctrl_partial_access.81832173
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.349876514
/workspace/coverage/default/12.sram_ctrl_ram_cfg.1840037325
/workspace/coverage/default/12.sram_ctrl_regwen.1828942355
/workspace/coverage/default/12.sram_ctrl_smoke.3973585327
/workspace/coverage/default/12.sram_ctrl_stress_all.1373088345
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/workspace/coverage/default/43.sram_ctrl_mem_walk.2458456895
/workspace/coverage/default/43.sram_ctrl_multiple_keys.1406032949
/workspace/coverage/default/43.sram_ctrl_partial_access.1308167379
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3155820993
/workspace/coverage/default/43.sram_ctrl_ram_cfg.686525188
/workspace/coverage/default/43.sram_ctrl_regwen.2958237328
/workspace/coverage/default/43.sram_ctrl_smoke.2086239448
/workspace/coverage/default/43.sram_ctrl_stress_all.1189648539
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.211715729
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.1705704528
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1262230785
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.1261134320
/workspace/coverage/default/44.sram_ctrl_alert_test.1295379709
/workspace/coverage/default/44.sram_ctrl_bijection.3157714371
/workspace/coverage/default/44.sram_ctrl_executable.711126021
/workspace/coverage/default/44.sram_ctrl_lc_escalation.2574881903
/workspace/coverage/default/44.sram_ctrl_max_throughput.3227126563
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.1663585646
/workspace/coverage/default/44.sram_ctrl_mem_walk.2624964024
/workspace/coverage/default/44.sram_ctrl_multiple_keys.3763351657
/workspace/coverage/default/44.sram_ctrl_partial_access.235804818
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2474248656
/workspace/coverage/default/44.sram_ctrl_ram_cfg.4049506414
/workspace/coverage/default/44.sram_ctrl_regwen.2598845872
/workspace/coverage/default/44.sram_ctrl_smoke.482463318
/workspace/coverage/default/44.sram_ctrl_stress_all.1507644323
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1165601592
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.3917363817
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3968812057
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3918571509
/workspace/coverage/default/45.sram_ctrl_alert_test.3624906365
/workspace/coverage/default/45.sram_ctrl_bijection.3645069649
/workspace/coverage/default/45.sram_ctrl_executable.3933038671
/workspace/coverage/default/45.sram_ctrl_lc_escalation.1986377736
/workspace/coverage/default/45.sram_ctrl_max_throughput.1905518009
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.649853308
/workspace/coverage/default/45.sram_ctrl_mem_walk.1761590224
/workspace/coverage/default/45.sram_ctrl_multiple_keys.463778627
/workspace/coverage/default/45.sram_ctrl_partial_access.1408427305
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2864677706
/workspace/coverage/default/45.sram_ctrl_ram_cfg.810732836
/workspace/coverage/default/45.sram_ctrl_regwen.2329614067
/workspace/coverage/default/45.sram_ctrl_smoke.1984988837
/workspace/coverage/default/45.sram_ctrl_stress_all.4255780658
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.108029221
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3094553874
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1337429691
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.2917640937
/workspace/coverage/default/46.sram_ctrl_alert_test.2829170867
/workspace/coverage/default/46.sram_ctrl_bijection.326558884
/workspace/coverage/default/46.sram_ctrl_executable.3383812263
/workspace/coverage/default/46.sram_ctrl_lc_escalation.759380845
/workspace/coverage/default/46.sram_ctrl_max_throughput.3390992266
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.3108104797
/workspace/coverage/default/46.sram_ctrl_mem_walk.3143908312
/workspace/coverage/default/46.sram_ctrl_multiple_keys.2317692228
/workspace/coverage/default/46.sram_ctrl_partial_access.1639583275
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3328926305
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3699022220
/workspace/coverage/default/46.sram_ctrl_regwen.145095909
/workspace/coverage/default/46.sram_ctrl_smoke.3882961229
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2344089796
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1923175730
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.515601319
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.4288441998
/workspace/coverage/default/47.sram_ctrl_alert_test.1997546291
/workspace/coverage/default/47.sram_ctrl_bijection.3815551903
/workspace/coverage/default/47.sram_ctrl_executable.3610085894
/workspace/coverage/default/47.sram_ctrl_lc_escalation.3788813645
/workspace/coverage/default/47.sram_ctrl_max_throughput.3323459460
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3548975568
/workspace/coverage/default/47.sram_ctrl_mem_walk.46921984
/workspace/coverage/default/47.sram_ctrl_multiple_keys.615349884
/workspace/coverage/default/47.sram_ctrl_partial_access.1512515483
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3511658818
/workspace/coverage/default/47.sram_ctrl_ram_cfg.2236429561
/workspace/coverage/default/47.sram_ctrl_regwen.2569865917
/workspace/coverage/default/47.sram_ctrl_smoke.468969975
/workspace/coverage/default/47.sram_ctrl_stress_all.4132106053
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3362075473
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.2631020223
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.338953015
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3091741513
/workspace/coverage/default/48.sram_ctrl_alert_test.907886326
/workspace/coverage/default/48.sram_ctrl_bijection.777190140
/workspace/coverage/default/48.sram_ctrl_executable.2172209169
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2792867109
/workspace/coverage/default/48.sram_ctrl_max_throughput.2082462340
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2868191965
/workspace/coverage/default/48.sram_ctrl_mem_walk.1487902610
/workspace/coverage/default/48.sram_ctrl_multiple_keys.643418619
/workspace/coverage/default/48.sram_ctrl_partial_access.2680972283
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1931096113
/workspace/coverage/default/48.sram_ctrl_ram_cfg.2624081821
/workspace/coverage/default/48.sram_ctrl_regwen.1668001669
/workspace/coverage/default/48.sram_ctrl_smoke.734891352
/workspace/coverage/default/48.sram_ctrl_stress_all.2377659959
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.235281676
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2910496964
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3248595521
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.3831495900
/workspace/coverage/default/49.sram_ctrl_alert_test.3671561208
/workspace/coverage/default/49.sram_ctrl_bijection.2467879698
/workspace/coverage/default/49.sram_ctrl_executable.1332955450
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2000135253
/workspace/coverage/default/49.sram_ctrl_max_throughput.1733583414
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3648240269
/workspace/coverage/default/49.sram_ctrl_mem_walk.181122459
/workspace/coverage/default/49.sram_ctrl_multiple_keys.681206251
/workspace/coverage/default/49.sram_ctrl_partial_access.1797406781
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.787229181
/workspace/coverage/default/49.sram_ctrl_ram_cfg.3076241880
/workspace/coverage/default/49.sram_ctrl_regwen.543105266
/workspace/coverage/default/49.sram_ctrl_smoke.4063217062
/workspace/coverage/default/49.sram_ctrl_stress_all.664790204
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3034800953
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.215193936
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.717951463
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.2405708464
/workspace/coverage/default/5.sram_ctrl_alert_test.3244272440
/workspace/coverage/default/5.sram_ctrl_bijection.990095903
/workspace/coverage/default/5.sram_ctrl_executable.3369651227
/workspace/coverage/default/5.sram_ctrl_lc_escalation.4264886429
/workspace/coverage/default/5.sram_ctrl_max_throughput.1556496533
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3398597321
/workspace/coverage/default/5.sram_ctrl_mem_walk.3370045726
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1828778577
/workspace/coverage/default/5.sram_ctrl_partial_access.2999514715
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.915578652
/workspace/coverage/default/5.sram_ctrl_ram_cfg.169480128
/workspace/coverage/default/5.sram_ctrl_regwen.3777760186
/workspace/coverage/default/5.sram_ctrl_smoke.3836439048
/workspace/coverage/default/5.sram_ctrl_stress_all.731717727
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2212373922
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3723250846
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2012823813
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1169420834
/workspace/coverage/default/6.sram_ctrl_alert_test.4110641609
/workspace/coverage/default/6.sram_ctrl_bijection.3774601203
/workspace/coverage/default/6.sram_ctrl_executable.1311297615
/workspace/coverage/default/6.sram_ctrl_lc_escalation.1803494119
/workspace/coverage/default/6.sram_ctrl_max_throughput.3412136554
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1121496186
/workspace/coverage/default/6.sram_ctrl_mem_walk.87464028
/workspace/coverage/default/6.sram_ctrl_multiple_keys.104657019
/workspace/coverage/default/6.sram_ctrl_partial_access.757020576
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2967936519
/workspace/coverage/default/6.sram_ctrl_ram_cfg.3212743993
/workspace/coverage/default/6.sram_ctrl_regwen.1475540146
/workspace/coverage/default/6.sram_ctrl_smoke.4130287623
/workspace/coverage/default/6.sram_ctrl_stress_all.1665880445
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1373963411
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3825607621
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1830559137
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.2816764804
/workspace/coverage/default/7.sram_ctrl_alert_test.31180455
/workspace/coverage/default/7.sram_ctrl_bijection.2923869822
/workspace/coverage/default/7.sram_ctrl_executable.1495332959
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2677820940
/workspace/coverage/default/7.sram_ctrl_max_throughput.2200147487
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.37289323
/workspace/coverage/default/7.sram_ctrl_mem_walk.1208753087
/workspace/coverage/default/7.sram_ctrl_multiple_keys.2270172576
/workspace/coverage/default/7.sram_ctrl_partial_access.540870401
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.4027381179
/workspace/coverage/default/7.sram_ctrl_ram_cfg.1240224377
/workspace/coverage/default/7.sram_ctrl_regwen.32325095
/workspace/coverage/default/7.sram_ctrl_smoke.3594658767
/workspace/coverage/default/7.sram_ctrl_stress_all.387990834
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1557394158
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1530961810
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1459334157
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.740390513
/workspace/coverage/default/8.sram_ctrl_alert_test.3255432575
/workspace/coverage/default/8.sram_ctrl_bijection.169199840
/workspace/coverage/default/8.sram_ctrl_executable.1267865588
/workspace/coverage/default/8.sram_ctrl_lc_escalation.449609031
/workspace/coverage/default/8.sram_ctrl_max_throughput.3065431082
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1694080341
/workspace/coverage/default/8.sram_ctrl_mem_walk.3969999801
/workspace/coverage/default/8.sram_ctrl_multiple_keys.2556208894
/workspace/coverage/default/8.sram_ctrl_partial_access.61028046
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3934462686
/workspace/coverage/default/8.sram_ctrl_ram_cfg.2989892290
/workspace/coverage/default/8.sram_ctrl_regwen.2234212471
/workspace/coverage/default/8.sram_ctrl_smoke.563892160
/workspace/coverage/default/8.sram_ctrl_stress_all.2884204242
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.864117897
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.2246996827
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1239552093
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.2984084639
/workspace/coverage/default/9.sram_ctrl_alert_test.1107693072
/workspace/coverage/default/9.sram_ctrl_bijection.1035098478
/workspace/coverage/default/9.sram_ctrl_executable.2987470214
/workspace/coverage/default/9.sram_ctrl_lc_escalation.389071704
/workspace/coverage/default/9.sram_ctrl_max_throughput.3763551076
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.722852134
/workspace/coverage/default/9.sram_ctrl_mem_walk.3361986080
/workspace/coverage/default/9.sram_ctrl_multiple_keys.2081184548
/workspace/coverage/default/9.sram_ctrl_partial_access.770349866
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3772319641
/workspace/coverage/default/9.sram_ctrl_ram_cfg.2524189581
/workspace/coverage/default/9.sram_ctrl_regwen.1645472385
/workspace/coverage/default/9.sram_ctrl_smoke.2049525873
/workspace/coverage/default/9.sram_ctrl_stress_all.2408352933
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1437131237
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.2676810950
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2138867458



Total test records in report: 1035
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/35.sram_ctrl_stress_pipeline.2417650785 Apr 23 12:25:07 PM PDT 24 Apr 23 12:27:50 PM PDT 24 7344644008 ps
T2 /workspace/coverage/default/45.sram_ctrl_mem_partial_access.649853308 Apr 23 12:25:31 PM PDT 24 Apr 23 12:25:34 PM PDT 24 607893084 ps
T3 /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3670279619 Apr 23 12:24:07 PM PDT 24 Apr 23 12:27:04 PM PDT 24 1528535081 ps
T7 /workspace/coverage/default/49.sram_ctrl_ram_cfg.3076241880 Apr 23 12:25:37 PM PDT 24 Apr 23 12:25:39 PM PDT 24 59811949 ps
T8 /workspace/coverage/default/41.sram_ctrl_regwen.1507009212 Apr 23 12:25:28 PM PDT 24 Apr 23 12:34:06 PM PDT 24 1501365531 ps
T9 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.1705704528 Apr 23 12:25:40 PM PDT 24 Apr 23 12:29:10 PM PDT 24 2457395476 ps
T4 /workspace/coverage/default/36.sram_ctrl_lc_escalation.2704358788 Apr 23 12:25:12 PM PDT 24 Apr 23 12:25:20 PM PDT 24 1955912274 ps
T5 /workspace/coverage/default/10.sram_ctrl_stress_all.1156378025 Apr 23 12:23:56 PM PDT 24 Apr 23 12:54:27 PM PDT 24 22837317416 ps
T10 /workspace/coverage/default/38.sram_ctrl_executable.133958254 Apr 23 12:25:09 PM PDT 24 Apr 23 12:41:51 PM PDT 24 13027124017 ps
T11 /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1830559137 Apr 23 12:23:33 PM PDT 24 Apr 23 12:23:38 PM PDT 24 226294875 ps
T14 /workspace/coverage/default/37.sram_ctrl_multiple_keys.3890126036 Apr 23 12:25:19 PM PDT 24 Apr 23 12:37:17 PM PDT 24 63420647319 ps
T49 /workspace/coverage/default/38.sram_ctrl_partial_access.2570934644 Apr 23 12:25:12 PM PDT 24 Apr 23 12:25:28 PM PDT 24 946315041 ps
T21 /workspace/coverage/default/14.sram_ctrl_regwen.3856058713 Apr 23 12:24:42 PM PDT 24 Apr 23 12:39:34 PM PDT 24 57461540033 ps
T12 /workspace/coverage/default/8.sram_ctrl_stress_all.2884204242 Apr 23 12:23:53 PM PDT 24 Apr 23 01:11:39 PM PDT 24 76816911132 ps
T38 /workspace/coverage/default/41.sram_ctrl_access_during_key_req.2588747002 Apr 23 12:25:24 PM PDT 24 Apr 23 12:35:42 PM PDT 24 4055474553 ps
T25 /workspace/coverage/default/14.sram_ctrl_ram_cfg.2095785585 Apr 23 12:24:18 PM PDT 24 Apr 23 12:24:19 PM PDT 24 50257068 ps
T143 /workspace/coverage/default/15.sram_ctrl_max_throughput.2501599591 Apr 23 12:24:11 PM PDT 24 Apr 23 12:26:19 PM PDT 24 139157891 ps
T22 /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3082355558 Apr 23 12:25:01 PM PDT 24 Apr 23 12:38:13 PM PDT 24 24048187948 ps
T137 /workspace/coverage/default/7.sram_ctrl_smoke.3594658767 Apr 23 12:23:47 PM PDT 24 Apr 23 12:23:57 PM PDT 24 178015504 ps
T13 /workspace/coverage/default/21.sram_ctrl_mem_partial_access.4264727734 Apr 23 12:24:37 PM PDT 24 Apr 23 12:24:42 PM PDT 24 183475034 ps
T39 /workspace/coverage/default/18.sram_ctrl_access_during_key_req.908471385 Apr 23 12:24:35 PM PDT 24 Apr 23 12:45:38 PM PDT 24 3203928715 ps
T41 /workspace/coverage/default/13.sram_ctrl_executable.1224254945 Apr 23 12:24:06 PM PDT 24 Apr 23 12:28:34 PM PDT 24 37316495178 ps
T6 /workspace/coverage/default/14.sram_ctrl_stress_all.731509204 Apr 23 12:24:08 PM PDT 24 Apr 23 12:53:56 PM PDT 24 40658566827 ps
T138 /workspace/coverage/default/22.sram_ctrl_smoke.494332667 Apr 23 12:24:35 PM PDT 24 Apr 23 12:24:46 PM PDT 24 1162852741 ps
T135 /workspace/coverage/default/17.sram_ctrl_partial_access.71463203 Apr 23 12:24:18 PM PDT 24 Apr 23 12:26:48 PM PDT 24 225925851 ps
T87 /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1058228566 Apr 23 12:24:38 PM PDT 24 Apr 23 12:28:42 PM PDT 24 14219167039 ps
T18 /workspace/coverage/default/34.sram_ctrl_alert_test.2305253950 Apr 23 12:25:08 PM PDT 24 Apr 23 12:25:14 PM PDT 24 68700696 ps
T144 /workspace/coverage/default/44.sram_ctrl_max_throughput.3227126563 Apr 23 12:25:40 PM PDT 24 Apr 23 12:27:39 PM PDT 24 1049044830 ps
T26 /workspace/coverage/default/45.sram_ctrl_ram_cfg.810732836 Apr 23 12:25:36 PM PDT 24 Apr 23 12:25:38 PM PDT 24 445431715 ps
T40 /workspace/coverage/default/21.sram_ctrl_access_during_key_req.1465464551 Apr 23 12:24:30 PM PDT 24 Apr 23 12:52:20 PM PDT 24 4187969893 ps
T23 /workspace/coverage/default/46.sram_ctrl_stress_all.1637726608 Apr 23 12:25:33 PM PDT 24 Apr 23 12:59:09 PM PDT 24 14425687043 ps
T145 /workspace/coverage/default/8.sram_ctrl_multiple_keys.2556208894 Apr 23 12:23:52 PM PDT 24 Apr 23 12:25:17 PM PDT 24 16448540954 ps
T130 /workspace/coverage/default/16.sram_ctrl_executable.2715209806 Apr 23 12:24:17 PM PDT 24 Apr 23 12:43:36 PM PDT 24 11244290999 ps
T88 /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.915578652 Apr 23 12:23:22 PM PDT 24 Apr 23 12:29:36 PM PDT 24 10013031046 ps
T146 /workspace/coverage/default/31.sram_ctrl_smoke.1674961893 Apr 23 12:24:53 PM PDT 24 Apr 23 12:24:58 PM PDT 24 253497776 ps
T67 /workspace/coverage/default/26.sram_ctrl_access_during_key_req.3319031644 Apr 23 12:24:54 PM PDT 24 Apr 23 12:43:43 PM PDT 24 8095833138 ps
T132 /workspace/coverage/default/44.sram_ctrl_executable.711126021 Apr 23 12:25:38 PM PDT 24 Apr 23 12:41:10 PM PDT 24 14230103303 ps
T68 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.2515645733 Apr 23 12:25:07 PM PDT 24 Apr 23 12:25:15 PM PDT 24 87192427 ps
T24 /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3129888397 Apr 23 12:24:36 PM PDT 24 Apr 23 12:43:16 PM PDT 24 2983733168 ps
T147 /workspace/coverage/default/42.sram_ctrl_ram_cfg.2593837612 Apr 23 12:25:24 PM PDT 24 Apr 23 12:25:26 PM PDT 24 33006057 ps
T69 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.319722902 Apr 23 12:24:57 PM PDT 24 Apr 23 12:25:01 PM PDT 24 170693715 ps
T148 /workspace/coverage/default/26.sram_ctrl_max_throughput.3040524190 Apr 23 12:24:53 PM PDT 24 Apr 23 12:25:03 PM PDT 24 63150648 ps
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T155 /workspace/coverage/default/30.sram_ctrl_partial_access.2770245895 Apr 23 12:24:47 PM PDT 24 Apr 23 12:24:54 PM PDT 24 344008134 ps
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T162 /workspace/coverage/default/6.sram_ctrl_partial_access.757020576 Apr 23 12:23:34 PM PDT 24 Apr 23 12:23:35 PM PDT 24 48740391 ps
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T164 /workspace/coverage/default/22.sram_ctrl_stress_all.2787248636 Apr 23 12:24:35 PM PDT 24 Apr 23 12:26:18 PM PDT 24 2204956691 ps
T165 /workspace/coverage/default/16.sram_ctrl_bijection.1893536840 Apr 23 12:24:36 PM PDT 24 Apr 23 12:25:37 PM PDT 24 1970742376 ps
T71 /workspace/coverage/default/40.sram_ctrl_mem_partial_access.712682386 Apr 23 12:25:19 PM PDT 24 Apr 23 12:25:25 PM PDT 24 66118844 ps
T20 /workspace/coverage/default/37.sram_ctrl_alert_test.1544553722 Apr 23 12:25:07 PM PDT 24 Apr 23 12:25:13 PM PDT 24 50367324 ps
T166 /workspace/coverage/default/35.sram_ctrl_ram_cfg.2273279459 Apr 23 12:25:11 PM PDT 24 Apr 23 12:25:16 PM PDT 24 28856658 ps
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T172 /workspace/coverage/default/28.sram_ctrl_stress_pipeline.3722786532 Apr 23 12:24:56 PM PDT 24 Apr 23 12:30:30 PM PDT 24 51925079663 ps
T173 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.2576704146 Apr 23 12:25:02 PM PDT 24 Apr 23 12:25:06 PM PDT 24 347376405 ps
T174 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.2337060285 Apr 23 12:24:37 PM PDT 24 Apr 23 12:24:42 PM PDT 24 48016761 ps
T175 /workspace/coverage/default/33.sram_ctrl_access_during_key_req.59786111 Apr 23 12:24:48 PM PDT 24 Apr 23 12:52:19 PM PDT 24 12183735193 ps
T176 /workspace/coverage/default/5.sram_ctrl_ram_cfg.169480128 Apr 23 12:23:23 PM PDT 24 Apr 23 12:23:25 PM PDT 24 50188657 ps
T177 /workspace/coverage/default/15.sram_ctrl_stress_all.1109035591 Apr 23 12:24:25 PM PDT 24 Apr 23 01:09:56 PM PDT 24 119412872131 ps
T44 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1751472799 Apr 23 12:24:40 PM PDT 24 Apr 23 12:25:13 PM PDT 24 6653461272 ps
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T179 /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1774808731 Apr 23 12:25:24 PM PDT 24 Apr 23 12:26:31 PM PDT 24 123191962 ps
T180 /workspace/coverage/default/44.sram_ctrl_alert_test.1295379709 Apr 23 12:25:23 PM PDT 24 Apr 23 12:25:25 PM PDT 24 36443240 ps
T181 /workspace/coverage/default/17.sram_ctrl_mem_partial_access.1968813412 Apr 23 12:24:48 PM PDT 24 Apr 23 12:24:51 PM PDT 24 120496435 ps
T182 /workspace/coverage/default/42.sram_ctrl_bijection.461764732 Apr 23 12:25:23 PM PDT 24 Apr 23 12:25:52 PM PDT 24 1765319753 ps
T183 /workspace/coverage/default/38.sram_ctrl_smoke.1801457402 Apr 23 12:25:00 PM PDT 24 Apr 23 12:25:17 PM PDT 24 766892739 ps
T184 /workspace/coverage/default/37.sram_ctrl_regwen.4218231184 Apr 23 12:25:14 PM PDT 24 Apr 23 12:52:09 PM PDT 24 11894461330 ps
T185 /workspace/coverage/default/26.sram_ctrl_mem_partial_access.2184323420 Apr 23 12:24:54 PM PDT 24 Apr 23 12:25:01 PM PDT 24 118547727 ps
T45 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3173599754 Apr 23 12:24:19 PM PDT 24 Apr 23 12:24:34 PM PDT 24 532901439 ps
T186 /workspace/coverage/default/13.sram_ctrl_multiple_keys.4184333505 Apr 23 12:24:36 PM PDT 24 Apr 23 12:54:13 PM PDT 24 3364296763 ps
T187 /workspace/coverage/default/3.sram_ctrl_partial_access.651751989 Apr 23 12:23:22 PM PDT 24 Apr 23 12:23:39 PM PDT 24 933115497 ps
T46 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.160510464 Apr 23 12:24:06 PM PDT 24 Apr 23 12:24:48 PM PDT 24 1511001278 ps
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T107 /workspace/coverage/default/14.sram_ctrl_mem_partial_access.3901840408 Apr 23 12:24:11 PM PDT 24 Apr 23 12:24:19 PM PDT 24 304110585 ps
T108 /workspace/coverage/default/31.sram_ctrl_stress_all.3019078029 Apr 23 12:25:06 PM PDT 24 Apr 23 01:23:34 PM PDT 24 65725194485 ps
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T110 /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.86489732 Apr 23 12:24:51 PM PDT 24 Apr 23 12:25:15 PM PDT 24 350178047 ps
T111 /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3300144933 Apr 23 12:25:07 PM PDT 24 Apr 23 12:32:40 PM PDT 24 253274540229 ps
T112 /workspace/coverage/default/30.sram_ctrl_stress_all.3461732349 Apr 23 12:24:49 PM PDT 24 Apr 23 01:51:41 PM PDT 24 23061936616 ps
T113 /workspace/coverage/default/42.sram_ctrl_max_throughput.1961702795 Apr 23 12:25:26 PM PDT 24 Apr 23 12:25:30 PM PDT 24 190142750 ps
T114 /workspace/coverage/default/22.sram_ctrl_ram_cfg.510025165 Apr 23 12:24:45 PM PDT 24 Apr 23 12:24:47 PM PDT 24 78283121 ps
T188 /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.4027381179 Apr 23 12:23:38 PM PDT 24 Apr 23 12:27:35 PM PDT 24 18962148677 ps
T189 /workspace/coverage/default/12.sram_ctrl_max_throughput.2667404655 Apr 23 12:24:13 PM PDT 24 Apr 23 12:24:21 PM PDT 24 220897273 ps
T190 /workspace/coverage/default/49.sram_ctrl_mem_partial_access.3648240269 Apr 23 12:25:41 PM PDT 24 Apr 23 12:25:45 PM PDT 24 174581186 ps
T191 /workspace/coverage/default/6.sram_ctrl_access_during_key_req.1169420834 Apr 23 12:23:36 PM PDT 24 Apr 23 12:42:41 PM PDT 24 31981787460 ps
T192 /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.13440283 Apr 23 12:25:05 PM PDT 24 Apr 23 12:25:52 PM PDT 24 259934720 ps
T193 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2864677706 Apr 23 12:25:29 PM PDT 24 Apr 23 12:31:38 PM PDT 24 54229608933 ps
T194 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.3108104797 Apr 23 12:25:44 PM PDT 24 Apr 23 12:25:50 PM PDT 24 121589401 ps
T195 /workspace/coverage/default/43.sram_ctrl_stress_all.1189648539 Apr 23 12:25:40 PM PDT 24 Apr 23 01:21:43 PM PDT 24 655635863046 ps
T196 /workspace/coverage/default/47.sram_ctrl_partial_access.1512515483 Apr 23 12:25:57 PM PDT 24 Apr 23 12:26:16 PM PDT 24 1071286775 ps
T197 /workspace/coverage/default/28.sram_ctrl_alert_test.1114687186 Apr 23 12:24:48 PM PDT 24 Apr 23 12:24:50 PM PDT 24 40552555 ps
T198 /workspace/coverage/default/49.sram_ctrl_smoke.4063217062 Apr 23 12:25:32 PM PDT 24 Apr 23 12:25:36 PM PDT 24 99462201 ps
T199 /workspace/coverage/default/5.sram_ctrl_executable.3369651227 Apr 23 12:23:23 PM PDT 24 Apr 23 12:39:40 PM PDT 24 19571126701 ps
T200 /workspace/coverage/default/40.sram_ctrl_max_throughput.3209326125 Apr 23 12:25:10 PM PDT 24 Apr 23 12:25:18 PM PDT 24 205646591 ps
T201 /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3968812057 Apr 23 12:25:18 PM PDT 24 Apr 23 12:25:55 PM PDT 24 125052391 ps
T202 /workspace/coverage/default/19.sram_ctrl_max_throughput.3449298989 Apr 23 12:24:40 PM PDT 24 Apr 23 12:25:03 PM PDT 24 94053957 ps
T203 /workspace/coverage/default/25.sram_ctrl_ram_cfg.1000036793 Apr 23 12:24:37 PM PDT 24 Apr 23 12:24:40 PM PDT 24 51464442 ps
T204 /workspace/coverage/default/36.sram_ctrl_mem_walk.1812906252 Apr 23 12:25:10 PM PDT 24 Apr 23 12:25:24 PM PDT 24 599661358 ps
T205 /workspace/coverage/default/8.sram_ctrl_access_during_key_req.740390513 Apr 23 12:23:58 PM PDT 24 Apr 23 12:39:41 PM PDT 24 7946674486 ps
T206 /workspace/coverage/default/49.sram_ctrl_regwen.543105266 Apr 23 12:25:36 PM PDT 24 Apr 23 12:37:05 PM PDT 24 42018219918 ps
T207 /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.338953015 Apr 23 12:25:34 PM PDT 24 Apr 23 12:28:00 PM PDT 24 142770539 ps
T208 /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1137648074 Apr 23 12:24:53 PM PDT 24 Apr 23 12:25:09 PM PDT 24 321171969 ps
T209 /workspace/coverage/default/29.sram_ctrl_multiple_keys.78532842 Apr 23 12:25:00 PM PDT 24 Apr 23 12:38:44 PM PDT 24 8751075668 ps
T210 /workspace/coverage/default/25.sram_ctrl_bijection.404426224 Apr 23 12:24:38 PM PDT 24 Apr 23 12:25:08 PM PDT 24 2619364766 ps
T211 /workspace/coverage/default/40.sram_ctrl_stress_pipeline.1942526321 Apr 23 12:25:07 PM PDT 24 Apr 23 12:28:35 PM PDT 24 8863196773 ps
T212 /workspace/coverage/default/39.sram_ctrl_max_throughput.3211657961 Apr 23 12:25:10 PM PDT 24 Apr 23 12:26:18 PM PDT 24 110231793 ps
T213 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2273637999 Apr 23 12:24:09 PM PDT 24 Apr 23 12:28:20 PM PDT 24 54962350790 ps
T214 /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.3038510792 Apr 23 12:24:54 PM PDT 24 Apr 23 12:25:06 PM PDT 24 86509577 ps
T215 /workspace/coverage/default/12.sram_ctrl_multiple_keys.1911287446 Apr 23 12:24:06 PM PDT 24 Apr 23 12:36:49 PM PDT 24 15433748739 ps
T216 /workspace/coverage/default/43.sram_ctrl_multiple_keys.1406032949 Apr 23 12:25:26 PM PDT 24 Apr 23 12:34:35 PM PDT 24 1952573393 ps
T47 /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1437131237 Apr 23 12:24:07 PM PDT 24 Apr 23 12:25:52 PM PDT 24 3419165531 ps
T217 /workspace/coverage/default/25.sram_ctrl_partial_access.393857207 Apr 23 12:24:35 PM PDT 24 Apr 23 12:24:55 PM PDT 24 3862162064 ps
T218 /workspace/coverage/default/7.sram_ctrl_access_during_key_req.2816764804 Apr 23 12:23:46 PM PDT 24 Apr 23 12:38:21 PM PDT 24 3316303669 ps
T219 /workspace/coverage/default/23.sram_ctrl_ram_cfg.44294478 Apr 23 12:24:52 PM PDT 24 Apr 23 12:24:54 PM PDT 24 29224931 ps
T220 /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2246996827 Apr 23 12:23:52 PM PDT 24 Apr 23 12:28:43 PM PDT 24 6577539830 ps
T221 /workspace/coverage/default/12.sram_ctrl_partial_access.81832173 Apr 23 12:23:59 PM PDT 24 Apr 23 12:24:02 PM PDT 24 34215951 ps
T222 /workspace/coverage/default/16.sram_ctrl_partial_access.2973962913 Apr 23 12:24:31 PM PDT 24 Apr 23 12:24:45 PM PDT 24 10649847655 ps
T48 /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.211715729 Apr 23 12:25:26 PM PDT 24 Apr 23 12:42:12 PM PDT 24 2075642521 ps
T223 /workspace/coverage/default/3.sram_ctrl_executable.3828253419 Apr 23 12:23:20 PM PDT 24 Apr 23 12:35:49 PM PDT 24 10037513444 ps
T224 /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3907552956 Apr 23 12:24:23 PM PDT 24 Apr 23 12:26:49 PM PDT 24 3204772387 ps
T225 /workspace/coverage/default/24.sram_ctrl_max_throughput.3887674619 Apr 23 12:24:37 PM PDT 24 Apr 23 12:26:21 PM PDT 24 531301138 ps
T226 /workspace/coverage/default/33.sram_ctrl_regwen.2152135799 Apr 23 12:25:05 PM PDT 24 Apr 23 12:32:40 PM PDT 24 54290315743 ps
T100 /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.793243975 Apr 23 12:25:07 PM PDT 24 Apr 23 12:26:00 PM PDT 24 2158754293 ps
T227 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.1961286446 Apr 23 12:24:36 PM PDT 24 Apr 23 12:26:28 PM PDT 24 9498585649 ps
T228 /workspace/coverage/default/20.sram_ctrl_mem_walk.3858172108 Apr 23 12:24:41 PM PDT 24 Apr 23 12:24:47 PM PDT 24 269013959 ps
T229 /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.271026066 Apr 23 12:25:05 PM PDT 24 Apr 23 12:29:27 PM PDT 24 603432699 ps
T230 /workspace/coverage/default/36.sram_ctrl_bijection.164723342 Apr 23 12:25:05 PM PDT 24 Apr 23 12:26:07 PM PDT 24 13377279436 ps
T231 /workspace/coverage/default/12.sram_ctrl_executable.2006559 Apr 23 12:24:40 PM PDT 24 Apr 23 12:33:11 PM PDT 24 14732455137 ps
T232 /workspace/coverage/default/1.sram_ctrl_multiple_keys.2611386046 Apr 23 12:24:03 PM PDT 24 Apr 23 12:47:45 PM PDT 24 9425616500 ps
T233 /workspace/coverage/default/0.sram_ctrl_alert_test.968028949 Apr 23 12:23:01 PM PDT 24 Apr 23 12:23:02 PM PDT 24 30538065 ps
T234 /workspace/coverage/default/31.sram_ctrl_mem_partial_access.2831146321 Apr 23 12:24:44 PM PDT 24 Apr 23 12:24:47 PM PDT 24 153326541 ps
T235 /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3436128151 Apr 23 12:25:13 PM PDT 24 Apr 23 12:27:33 PM PDT 24 322043942 ps
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T237 /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2631020223 Apr 23 12:25:42 PM PDT 24 Apr 23 12:27:50 PM PDT 24 1439326669 ps
T238 /workspace/coverage/default/15.sram_ctrl_partial_access.595511977 Apr 23 12:24:19 PM PDT 24 Apr 23 12:24:31 PM PDT 24 11269054019 ps
T239 /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1914282614 Apr 23 12:25:17 PM PDT 24 Apr 23 12:25:29 PM PDT 24 133105348 ps
T240 /workspace/coverage/default/38.sram_ctrl_max_throughput.2333412434 Apr 23 12:25:10 PM PDT 24 Apr 23 12:25:16 PM PDT 24 117640902 ps
T101 /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3422143976 Apr 23 12:24:35 PM PDT 24 Apr 23 12:24:49 PM PDT 24 902249251 ps
T241 /workspace/coverage/default/4.sram_ctrl_access_during_key_req.2040776656 Apr 23 12:23:12 PM PDT 24 Apr 23 12:35:58 PM PDT 24 14654603236 ps
T242 /workspace/coverage/default/17.sram_ctrl_access_during_key_req.1663805357 Apr 23 12:24:21 PM PDT 24 Apr 23 12:37:20 PM PDT 24 5044393525 ps
T243 /workspace/coverage/default/13.sram_ctrl_alert_test.2245696259 Apr 23 12:24:16 PM PDT 24 Apr 23 12:24:18 PM PDT 24 11737635 ps
T244 /workspace/coverage/default/14.sram_ctrl_executable.2487223875 Apr 23 12:24:08 PM PDT 24 Apr 23 12:32:01 PM PDT 24 10478383798 ps
T245 /workspace/coverage/default/5.sram_ctrl_lc_escalation.4264886429 Apr 23 12:23:23 PM PDT 24 Apr 23 12:23:27 PM PDT 24 1173454364 ps
T246 /workspace/coverage/default/15.sram_ctrl_alert_test.257550560 Apr 23 12:24:21 PM PDT 24 Apr 23 12:24:23 PM PDT 24 15114950 ps
T247 /workspace/coverage/default/35.sram_ctrl_partial_access.3237644885 Apr 23 12:24:56 PM PDT 24 Apr 23 12:25:19 PM PDT 24 2246836951 ps
T248 /workspace/coverage/default/10.sram_ctrl_alert_test.1268994985 Apr 23 12:24:09 PM PDT 24 Apr 23 12:24:12 PM PDT 24 72642306 ps
T249 /workspace/coverage/default/23.sram_ctrl_regwen.3195432439 Apr 23 12:24:53 PM PDT 24 Apr 23 12:29:52 PM PDT 24 1147921986 ps
T250 /workspace/coverage/default/16.sram_ctrl_regwen.3644262125 Apr 23 12:24:09 PM PDT 24 Apr 23 12:41:37 PM PDT 24 67102304506 ps
T251 /workspace/coverage/default/47.sram_ctrl_access_during_key_req.4288441998 Apr 23 12:25:44 PM PDT 24 Apr 23 12:31:10 PM PDT 24 3065392849 ps
T252 /workspace/coverage/default/24.sram_ctrl_executable.3527547982 Apr 23 12:24:22 PM PDT 24 Apr 23 12:28:02 PM PDT 24 7700186512 ps
T253 /workspace/coverage/default/2.sram_ctrl_stress_all.2410443268 Apr 23 12:23:45 PM PDT 24 Apr 23 01:00:38 PM PDT 24 7297043398 ps
T254 /workspace/coverage/default/13.sram_ctrl_stress_pipeline.2463494821 Apr 23 12:24:09 PM PDT 24 Apr 23 12:29:10 PM PDT 24 20048723665 ps
T255 /workspace/coverage/default/0.sram_ctrl_stress_pipeline.1828307361 Apr 23 12:24:12 PM PDT 24 Apr 23 12:27:52 PM PDT 24 5195215896 ps
T256 /workspace/coverage/default/26.sram_ctrl_partial_access.919058210 Apr 23 12:24:51 PM PDT 24 Apr 23 12:25:09 PM PDT 24 933706587 ps
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T258 /workspace/coverage/default/11.sram_ctrl_smoke.3420028971 Apr 23 12:23:59 PM PDT 24 Apr 23 12:24:10 PM PDT 24 3074480593 ps
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T293 /workspace/coverage/default/26.sram_ctrl_ram_cfg.2002417369 Apr 23 12:24:54 PM PDT 24 Apr 23 12:24:57 PM PDT 24 85444687 ps
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T298 /workspace/coverage/default/29.sram_ctrl_lc_escalation.3217398895 Apr 23 12:25:07 PM PDT 24 Apr 23 12:25:16 PM PDT 24 432780305 ps
T299 /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3488305884 Apr 23 12:24:35 PM PDT 24 Apr 23 12:30:07 PM PDT 24 54305985148 ps
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T301 /workspace/coverage/default/0.sram_ctrl_ram_cfg.1163262823 Apr 23 12:24:09 PM PDT 24 Apr 23 12:24:12 PM PDT 24 82652353 ps
T302 /workspace/coverage/default/13.sram_ctrl_stress_all.273442610 Apr 23 12:24:19 PM PDT 24 Apr 23 01:48:29 PM PDT 24 69151736709 ps
T303 /workspace/coverage/default/10.sram_ctrl_executable.101313988 Apr 23 12:24:13 PM PDT 24 Apr 23 12:35:09 PM PDT 24 9959555815 ps
T304 /workspace/coverage/default/23.sram_ctrl_partial_access.3986104033 Apr 23 12:24:36 PM PDT 24 Apr 23 12:24:47 PM PDT 24 786796389 ps
T305 /workspace/coverage/default/33.sram_ctrl_ram_cfg.576549008 Apr 23 12:25:03 PM PDT 24 Apr 23 12:25:05 PM PDT 24 88348590 ps
T306 /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3748675159 Apr 23 12:25:00 PM PDT 24 Apr 23 12:25:20 PM PDT 24 88972921 ps
T307 /workspace/coverage/default/32.sram_ctrl_lc_escalation.2294080046 Apr 23 12:24:53 PM PDT 24 Apr 23 12:24:57 PM PDT 24 276347889 ps
T308 /workspace/coverage/default/4.sram_ctrl_executable.717504427 Apr 23 12:24:28 PM PDT 24 Apr 23 12:26:50 PM PDT 24 3555331428 ps
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