Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	46797068	1			T1	130381		T2	47		T3	20682
triple_byte_access	2567204	1			T1	2590		T2	118		T3	359
halfword_access	3852331	1			T1	3878		T2	228		T3	502
byte_access	5143378	1			T1	5169		T2	387		T3	737
zero_access	1292637	1			T1	1290		T2	182		T3	184

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29767952

1

T1

71733

T2

360

T3

10605

auto[1]

29884666

1

T1

71575

T2

602

T3

11859

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	23342214	1			T1	65238		T2	3		T3	9722
auto[0]	triple_byte_access	1280595	1			T1	1290		T2	11		T3	192
auto[0]	halfword_access	1923169	1			T1	1937		T2	56		T3	261
auto[0]	byte_access	2570363	1			T1	2600		T2	157		T3	350
auto[0]	zero_access	651611	1			T1	668		T2	133		T3	80
auto[1]	word_access	23454854	1			T1	65143		T2	44		T3	10960
auto[1]	triple_byte_access	1286609	1			T1	1300		T2	107		T3	167
auto[1]	halfword_access	1929162	1			T1	1941		T2	172		T3	241
auto[1]	byte_access	2573015	1			T1	2569		T2	230		T3	387
auto[1]	zero_access	641026	1			T1	622		T2	49		T3	104