Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	144703468	1			T1	6856		T2	94208		T3	18762
instr_valid_dis	112555117	1			T1	6856		T2	94208		T3	18762
instr_en	22477235	1			T19	82		T15	820300		T20	346768

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11652698	1			T19	38458		T15	235936		T20	17798
sram_ifetch_valid_disable	109843555	1			T1	6856		T2	94208		T3	18762
sram_ifetch_enable	23207215	1			T19	134582		T15	723666		T20	155700

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	144703468	1			T1	6856		T2	94208		T3	18762
hw_debug_en_valid_off	112405715	1			T1	6856		T2	94208		T3	18762
hw_debug_en_on	21739110	1			T19	102366		T15	616992		T20	144342

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	109843555	1			T1	6856		T2	94208		T3	18762
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	97461875	1			T1	6856		T2	94208		T3	18762
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8839695	1			T15	252018		T20	173270		T149	49810
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4914680	1			T15	79972		T20	17798		T60	352
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1403758	1			T15	62564		T60	352		T151	4692
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2555448	1			T15	17408		T20	17798		T29	3682
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	5025536	1			T19	38458		T15	155964		T60	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2673490	1			T15	108598		T60	20000		T149	34476
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1500474	1			T15	47366		T29	8114		T51	27008
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7860923	1			T15	207144		T20	125474		T149	60300
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3251936	1			T15	69218		T149	60300		T151	70072
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3382269	1			T15	137926		T20	125474		T64	13386

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8893052	1			T19	82		T15	503508		T20	155700
lc_exec_en	8852651	1			T19	63908		T15	253884		T20	18868
valid_exec_dis	108273604	1			T1	6856		T2	94208		T3	18762
invalid_exec_dis	34859913	1			T19	173040		T15	959602		T20	173498