Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	42743160	1			T1	3428		T2	47104		T3	8497
triple_byte_access	2498181	1			T3	172		T4	23638		T5	126
halfword_access	3751907	1			T3	280		T4	35367		T5	226
byte_access	5008035	1			T3	345		T4	47257		T5	381
zero_access	1261245	1			T3	87		T4	11955		T5	187

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27589667

1

T1

1674

T2

23552

T3

4705

auto[1]

27672861

1

T1

1754

T2

23552

T3

4676

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21334609	1			T1	1674		T2	23552		T3	4259
auto[0]	triple_byte_access	1246658	1			T3	81		T4	11686		T5	12
auto[0]	halfword_access	1871702	1			T3	148		T4	17651		T5	44
auto[0]	byte_access	2501679	1			T3	167		T4	23751		T5	179
auto[0]	zero_access	635019	1			T3	50		T4	5880		T5	131
auto[1]	word_access	21408551	1			T1	1754		T2	23552		T3	4238
auto[1]	triple_byte_access	1251523	1			T3	91		T4	11952		T5	114
auto[1]	halfword_access	1880205	1			T3	132		T4	17716		T5	182
auto[1]	byte_access	2506356	1			T3	178		T4	23506		T5	202
auto[1]	zero_access	626226	1			T3	37		T4	6075		T5	56