Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	149597776	1			T2	3076		T3	300276		T4	489150
instr_valid_dis	115644148	1			T2	3076		T3	300276		T4	489150
instr_en	24517040	1			T16	124586		T23	53426		T24	263998

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10916835	1			T3	72404		T16	61408		T23	117898
sram_ifetch_valid_disable	114431460	1			T2	3076		T3	22876		T4	489150
sram_ifetch_enable	24249481	1			T3	204996		T16	23117		T18	189300

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	149597776	1			T2	3076		T3	300276		T4	489150
hw_debug_en_valid_off	118094268	1			T2	3076		T3	113148		T4	489150
hw_debug_en_on	20568710	1			T3	164678		T16	50607		T18	89980

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	114431460	1			T2	3076		T3	22876		T4	489150
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	101831224	1			T2	3076		T3	22876		T4	489150
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9075741	1			T16	50973		T23	33840		T24	68146
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5383475	1			T3	32654		T16	6442		T23	11868
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1956678	1			T3	32654		T16	6442		T23	11868
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2607728	1			T39	46792		T37	30324		T124	17426
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3542720	1			T3	39750		T16	10088		T23	37702
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1495266	1			T3	39750		T23	18116		T51	29368
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1442008	1			T16	10088		T23	19586		T24	63936
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7759419	1			T3	22876		T16	36049		T18	38454
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3105366	1			T3	22876		T16	7242		T23	6902
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3267903	1			T16	28807		T23	22020		T24	57324

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10498211	1			T16	18647		T24	111916		T39	212352
lc_exec_en	9266571	1			T3	102052		T16	4470		T18	51526
valid_exec_dis	111844361	1			T2	3076		T3	204996		T4	489150
invalid_exec_dis	35166316	1			T3	277400		T16	84525		T18	189300