Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.08 99.81 96.99 100.00 100.00 98.57 99.70 98.52


Total tests in report: 1023
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
77.67 77.67 97.37 97.37 79.74 79.74 64.02 64.02 71.43 71.43 90.20 90.20 94.90 94.90 46.01 46.01 /workspace/coverage/default/7.sram_ctrl_regwen.4052993855
88.66 11.00 97.95 0.58 84.68 4.94 96.14 32.12 71.43 0.00 91.64 1.44 96.25 1.35 82.56 36.55 /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.33163709
95.07 6.41 99.32 1.36 89.61 4.94 96.49 0.36 100.00 28.57 96.25 4.61 96.25 0.00 87.57 5.01 /workspace/coverage/default/36.sram_ctrl_stress_all.2746073735
96.11 1.04 99.51 0.19 90.26 0.65 96.71 0.21 100.00 0.00 97.12 0.86 96.25 0.00 92.95 5.38 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.915397838
96.88 0.77 99.51 0.00 91.43 1.17 98.43 1.72 100.00 0.00 97.98 0.86 96.40 0.15 94.43 1.48 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3096139240
97.63 0.75 99.71 0.19 93.38 1.95 99.14 0.72 100.00 0.00 98.85 0.86 97.00 0.60 95.36 0.93 /workspace/coverage/default/2.sram_ctrl_sec_cm.2131642198
97.87 0.24 99.71 0.00 93.64 0.26 99.21 0.07 100.00 0.00 98.85 0.00 98.35 1.35 95.36 0.00 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1691592765
98.09 0.21 99.71 0.00 93.64 0.00 99.21 0.00 100.00 0.00 98.85 0.00 98.35 0.00 96.85 1.48 /workspace/coverage/default/24.sram_ctrl_stress_all.2204728980
98.23 0.15 99.71 0.00 93.77 0.13 99.21 0.00 100.00 0.00 98.85 0.00 99.25 0.90 96.85 0.00 /workspace/coverage/default/0.sram_ctrl_access_during_key_req.3693567948
98.35 0.12 99.81 0.10 93.77 0.00 99.93 0.72 100.00 0.00 98.85 0.00 99.25 0.00 96.85 0.00 /workspace/coverage/default/1.sram_ctrl_ram_cfg.808043801
98.43 0.08 99.81 0.00 93.77 0.00 99.93 0.00 100.00 0.00 98.85 0.00 99.25 0.00 97.40 0.56 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3030140596
98.49 0.07 99.81 0.00 94.16 0.39 100.00 0.07 100.00 0.00 98.85 0.00 99.25 0.00 97.40 0.00 /workspace/coverage/default/0.sram_ctrl_alert_test.3447352739
98.56 0.06 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.70 0.45 97.40 0.00 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.409786029
98.61 0.05 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.70 0.00 97.77 0.37 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4196045971
98.66 0.05 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.70 0.00 98.14 0.37 /workspace/coverage/default/2.sram_ctrl_executable.1661782713
98.69 0.03 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.70 0.00 98.33 0.19 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.602639372
98.72 0.03 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.70 0.00 98.52 0.19 /workspace/coverage/default/23.sram_ctrl_lc_escalation.3882648354

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4060598496
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2700394505
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3330235747
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.379881932
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1264395732
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1668714302
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3544525491
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3526809251
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3045513090
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2904256718
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.825728386
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.925081257
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2813921976
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.306334981
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.232867324
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2719231430
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.453175753
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3227180062
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1806916471
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3176756034
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.734582547
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1613997586
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1308923314
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3265071724
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3457093366
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3739399518
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1300642627
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1455292342
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2194826979
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3884706216
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1395226636
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3045149232
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3711482347
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2371433884
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1178414877
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1942829302
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1705585186
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3988144562
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1402647309
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2906816794
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.4257774547
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.363560466
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3555070239
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1339936560
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2351304983
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.862946709
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2320260132
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1720202581
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3965470844
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3295821382
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2296020005
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3716435219
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.414591257
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3517641343
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2457613624
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2520690066
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1911788591
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1766289971
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.988047074
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3318691057
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.281269744
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3004607921
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.324307220
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1008235254
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.647872743
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.4059812612
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.670883652
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3751638264
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2940507055
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3634772983
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.64765873
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3382949278
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2527341097
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1743316822
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.96562856
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2938001059
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2929346584
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3716971223
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.947963272
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1601222183
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1377576102
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3798090217
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.99963490
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.204982230
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.668084777
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1170000813
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.4246995499
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.135679257
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3651156113
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1424465122
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2270431072
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.734331109
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.75599232
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3476891688
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3175787879
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1409298129
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2265375945
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.832596958
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3626531224
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3421074846
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3452533955
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3689680852
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1349576370
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.17694246
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.167449217
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2434815348
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3734388147
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3757113145
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3117128416
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1332616385
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3511691249
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2637918446
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.4050733577
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3993903181
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3216593408
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.71822787
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1440522906
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2028483173
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.62287325
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3641036978
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2851178926
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1277613689
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1817727995
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1593260989
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1991118634
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2521746735
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1415228924
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1649691847
/workspace/coverage/default/0.sram_ctrl_bijection.2689903530
/workspace/coverage/default/0.sram_ctrl_executable.759039783
/workspace/coverage/default/0.sram_ctrl_lc_escalation.1879421895
/workspace/coverage/default/0.sram_ctrl_max_throughput.270383933
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1418317440
/workspace/coverage/default/0.sram_ctrl_mem_walk.1840680459
/workspace/coverage/default/0.sram_ctrl_multiple_keys.2908371738
/workspace/coverage/default/0.sram_ctrl_partial_access.637786626
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2927299779
/workspace/coverage/default/0.sram_ctrl_ram_cfg.649021641
/workspace/coverage/default/0.sram_ctrl_regwen.223777170
/workspace/coverage/default/0.sram_ctrl_sec_cm.779510826
/workspace/coverage/default/0.sram_ctrl_smoke.4025333425
/workspace/coverage/default/0.sram_ctrl_stress_all.3282813893
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2233270619
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3796089138
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.878825290
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.502151046
/workspace/coverage/default/1.sram_ctrl_alert_test.3326171430
/workspace/coverage/default/1.sram_ctrl_bijection.3518060875
/workspace/coverage/default/1.sram_ctrl_executable.2789803194
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3948245171
/workspace/coverage/default/1.sram_ctrl_max_throughput.443832451
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3030710520
/workspace/coverage/default/1.sram_ctrl_mem_walk.1410353990
/workspace/coverage/default/1.sram_ctrl_multiple_keys.1748043231
/workspace/coverage/default/1.sram_ctrl_partial_access.3471378639
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.694988930
/workspace/coverage/default/1.sram_ctrl_regwen.2799060766
/workspace/coverage/default/1.sram_ctrl_sec_cm.3659151286
/workspace/coverage/default/1.sram_ctrl_smoke.828192466
/workspace/coverage/default/1.sram_ctrl_stress_all.3606861949
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.196472789
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.17401866
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3028999982
/workspace/coverage/default/10.sram_ctrl_alert_test.2839597915
/workspace/coverage/default/10.sram_ctrl_bijection.1703702202
/workspace/coverage/default/10.sram_ctrl_executable.2127850000
/workspace/coverage/default/10.sram_ctrl_lc_escalation.2226476223
/workspace/coverage/default/10.sram_ctrl_max_throughput.1314044884
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3875530968
/workspace/coverage/default/10.sram_ctrl_mem_walk.679806796
/workspace/coverage/default/10.sram_ctrl_multiple_keys.2931873580
/workspace/coverage/default/10.sram_ctrl_partial_access.2221484266
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2061716561
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1124675999
/workspace/coverage/default/10.sram_ctrl_regwen.1776157802
/workspace/coverage/default/10.sram_ctrl_smoke.4223111502
/workspace/coverage/default/10.sram_ctrl_stress_all.399729744
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3109201905
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.76827263
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.694534300
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2298282252
/workspace/coverage/default/11.sram_ctrl_alert_test.3101261089
/workspace/coverage/default/11.sram_ctrl_bijection.2177475458
/workspace/coverage/default/11.sram_ctrl_executable.1222384486
/workspace/coverage/default/11.sram_ctrl_lc_escalation.2232003059
/workspace/coverage/default/11.sram_ctrl_max_throughput.1385730974
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.912080856
/workspace/coverage/default/11.sram_ctrl_mem_walk.2650126076
/workspace/coverage/default/11.sram_ctrl_multiple_keys.1714169166
/workspace/coverage/default/11.sram_ctrl_partial_access.4028251271
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3769452330
/workspace/coverage/default/11.sram_ctrl_ram_cfg.422482221
/workspace/coverage/default/11.sram_ctrl_regwen.445332848
/workspace/coverage/default/11.sram_ctrl_smoke.593891806
/workspace/coverage/default/11.sram_ctrl_stress_all.3037560312
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.56952674
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.1446202491
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.391958597
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.2691489845
/workspace/coverage/default/12.sram_ctrl_alert_test.517878954
/workspace/coverage/default/12.sram_ctrl_bijection.2968414831
/workspace/coverage/default/12.sram_ctrl_executable.2772919191
/workspace/coverage/default/12.sram_ctrl_lc_escalation.2551740016
/workspace/coverage/default/12.sram_ctrl_max_throughput.627578710
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.2754727529
/workspace/coverage/default/12.sram_ctrl_mem_walk.2842059951
/workspace/coverage/default/12.sram_ctrl_multiple_keys.1334745545
/workspace/coverage/default/12.sram_ctrl_partial_access.967938789
/workspace/coverage/default/12.sram_ctrl_ram_cfg.2869850332
/workspace/coverage/default/12.sram_ctrl_regwen.1818319042
/workspace/coverage/default/12.sram_ctrl_smoke.313119102
/workspace/coverage/default/12.sram_ctrl_stress_all.3278866277
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2284310076
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/workspace/coverage/default/43.sram_ctrl_regwen.3835263891
/workspace/coverage/default/43.sram_ctrl_smoke.2673864188
/workspace/coverage/default/43.sram_ctrl_stress_all.2840411790
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.1715211623
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3818244030
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.1677085898
/workspace/coverage/default/44.sram_ctrl_alert_test.1425500390
/workspace/coverage/default/44.sram_ctrl_bijection.44435351
/workspace/coverage/default/44.sram_ctrl_executable.1111072877
/workspace/coverage/default/44.sram_ctrl_lc_escalation.2956960899
/workspace/coverage/default/44.sram_ctrl_max_throughput.3446732640
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.3287914183
/workspace/coverage/default/44.sram_ctrl_mem_walk.2599830937
/workspace/coverage/default/44.sram_ctrl_multiple_keys.3581379618
/workspace/coverage/default/44.sram_ctrl_partial_access.1287847384
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3462412691
/workspace/coverage/default/44.sram_ctrl_ram_cfg.815384372
/workspace/coverage/default/44.sram_ctrl_regwen.1590315370
/workspace/coverage/default/44.sram_ctrl_smoke.2667519594
/workspace/coverage/default/44.sram_ctrl_stress_all.1209544449
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.717169272
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.699479363
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2165334038
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3443297998
/workspace/coverage/default/45.sram_ctrl_alert_test.333143555
/workspace/coverage/default/45.sram_ctrl_bijection.2889017800
/workspace/coverage/default/45.sram_ctrl_executable.1584550980
/workspace/coverage/default/45.sram_ctrl_lc_escalation.1139939634
/workspace/coverage/default/45.sram_ctrl_max_throughput.1875511467
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.2032199739
/workspace/coverage/default/45.sram_ctrl_mem_walk.2669389707
/workspace/coverage/default/45.sram_ctrl_multiple_keys.3652603271
/workspace/coverage/default/45.sram_ctrl_partial_access.4060900558
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.4237130385
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1882187423
/workspace/coverage/default/45.sram_ctrl_regwen.4127748975
/workspace/coverage/default/45.sram_ctrl_smoke.2160361598
/workspace/coverage/default/45.sram_ctrl_stress_all.3729047515
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.748314446
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3231442823
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1261455641
/workspace/coverage/default/46.sram_ctrl_alert_test.2082070730
/workspace/coverage/default/46.sram_ctrl_bijection.635716347
/workspace/coverage/default/46.sram_ctrl_executable.693428038
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3121446854
/workspace/coverage/default/46.sram_ctrl_max_throughput.328022049
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.3117232711
/workspace/coverage/default/46.sram_ctrl_mem_walk.3036614760
/workspace/coverage/default/46.sram_ctrl_multiple_keys.4152247929
/workspace/coverage/default/46.sram_ctrl_partial_access.3368914250
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.793438323
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3327830759
/workspace/coverage/default/46.sram_ctrl_regwen.992505417
/workspace/coverage/default/46.sram_ctrl_smoke.1979942344
/workspace/coverage/default/46.sram_ctrl_stress_all.1429160124
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.402788505
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3322377018
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1335775775
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.2819928810
/workspace/coverage/default/47.sram_ctrl_alert_test.2238517771
/workspace/coverage/default/47.sram_ctrl_bijection.638958399
/workspace/coverage/default/47.sram_ctrl_executable.3748442981
/workspace/coverage/default/47.sram_ctrl_lc_escalation.183633705
/workspace/coverage/default/47.sram_ctrl_max_throughput.2444176397
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3163268408
/workspace/coverage/default/47.sram_ctrl_mem_walk.4272233198
/workspace/coverage/default/47.sram_ctrl_multiple_keys.2177185578
/workspace/coverage/default/47.sram_ctrl_partial_access.4285532521
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2470001196
/workspace/coverage/default/47.sram_ctrl_ram_cfg.3479972719
/workspace/coverage/default/47.sram_ctrl_regwen.626609521
/workspace/coverage/default/47.sram_ctrl_smoke.597904544
/workspace/coverage/default/47.sram_ctrl_stress_all.4193157744
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.2844979483
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3228612797
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.579529428
/workspace/coverage/default/48.sram_ctrl_alert_test.283551228
/workspace/coverage/default/48.sram_ctrl_bijection.3467551139
/workspace/coverage/default/48.sram_ctrl_executable.2805382799
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2844042873
/workspace/coverage/default/48.sram_ctrl_max_throughput.1221055597
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2452660692
/workspace/coverage/default/48.sram_ctrl_mem_walk.3592169171
/workspace/coverage/default/48.sram_ctrl_multiple_keys.946891626
/workspace/coverage/default/48.sram_ctrl_partial_access.1021767228
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2840553267
/workspace/coverage/default/48.sram_ctrl_ram_cfg.868838312
/workspace/coverage/default/48.sram_ctrl_regwen.602541109
/workspace/coverage/default/48.sram_ctrl_smoke.2498503353
/workspace/coverage/default/48.sram_ctrl_stress_all.363714542
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1087623287
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1195009457
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.1175085509
/workspace/coverage/default/49.sram_ctrl_alert_test.1040180949
/workspace/coverage/default/49.sram_ctrl_bijection.266596741
/workspace/coverage/default/49.sram_ctrl_executable.1225353367
/workspace/coverage/default/49.sram_ctrl_lc_escalation.3429501004
/workspace/coverage/default/49.sram_ctrl_max_throughput.3791654025
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.604690927
/workspace/coverage/default/49.sram_ctrl_mem_walk.2359497745
/workspace/coverage/default/49.sram_ctrl_multiple_keys.202393670
/workspace/coverage/default/49.sram_ctrl_partial_access.2750570836
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1174633104
/workspace/coverage/default/49.sram_ctrl_ram_cfg.211942418
/workspace/coverage/default/49.sram_ctrl_regwen.547950283
/workspace/coverage/default/49.sram_ctrl_smoke.3721356025
/workspace/coverage/default/49.sram_ctrl_stress_all.10826324
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2722178894
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1511222778
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.800769806
/workspace/coverage/default/5.sram_ctrl_alert_test.2940100821
/workspace/coverage/default/5.sram_ctrl_bijection.3165240712
/workspace/coverage/default/5.sram_ctrl_executable.269730548
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2268887183
/workspace/coverage/default/5.sram_ctrl_max_throughput.4131740222
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2835549566
/workspace/coverage/default/5.sram_ctrl_mem_walk.3701986331
/workspace/coverage/default/5.sram_ctrl_multiple_keys.693715009
/workspace/coverage/default/5.sram_ctrl_partial_access.213548465
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3686181313
/workspace/coverage/default/5.sram_ctrl_ram_cfg.1098639520
/workspace/coverage/default/5.sram_ctrl_regwen.1447881612
/workspace/coverage/default/5.sram_ctrl_smoke.360580468
/workspace/coverage/default/5.sram_ctrl_stress_all.1867459893
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3252985686
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3940137285
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2158748118
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1856756030
/workspace/coverage/default/6.sram_ctrl_alert_test.3747189471
/workspace/coverage/default/6.sram_ctrl_bijection.1026357387
/workspace/coverage/default/6.sram_ctrl_executable.1171403295
/workspace/coverage/default/6.sram_ctrl_lc_escalation.191219088
/workspace/coverage/default/6.sram_ctrl_max_throughput.3128561176
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3631275473
/workspace/coverage/default/6.sram_ctrl_mem_walk.1103075130
/workspace/coverage/default/6.sram_ctrl_multiple_keys.4157430549
/workspace/coverage/default/6.sram_ctrl_partial_access.3728237139
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.4032267140
/workspace/coverage/default/6.sram_ctrl_ram_cfg.3818174313
/workspace/coverage/default/6.sram_ctrl_regwen.3489512579
/workspace/coverage/default/6.sram_ctrl_smoke.776774529
/workspace/coverage/default/6.sram_ctrl_stress_all.2909950325
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.4239783237
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2548584451
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2920487907
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1280942044
/workspace/coverage/default/7.sram_ctrl_alert_test.3449076620
/workspace/coverage/default/7.sram_ctrl_bijection.2274720876
/workspace/coverage/default/7.sram_ctrl_executable.1163811309
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2725907341
/workspace/coverage/default/7.sram_ctrl_max_throughput.2708246244
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.667114008
/workspace/coverage/default/7.sram_ctrl_mem_walk.1046889030
/workspace/coverage/default/7.sram_ctrl_multiple_keys.520180895
/workspace/coverage/default/7.sram_ctrl_partial_access.3658517255
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3649045437
/workspace/coverage/default/7.sram_ctrl_ram_cfg.3238990356
/workspace/coverage/default/7.sram_ctrl_smoke.1571378021
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3599894132
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.374363661
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3574892329
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.511518069
/workspace/coverage/default/8.sram_ctrl_alert_test.167247205
/workspace/coverage/default/8.sram_ctrl_bijection.2706478658
/workspace/coverage/default/8.sram_ctrl_executable.2679490935
/workspace/coverage/default/8.sram_ctrl_lc_escalation.4293002214
/workspace/coverage/default/8.sram_ctrl_max_throughput.969785999
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.2638020329
/workspace/coverage/default/8.sram_ctrl_mem_walk.3242623358
/workspace/coverage/default/8.sram_ctrl_multiple_keys.2086178699
/workspace/coverage/default/8.sram_ctrl_partial_access.3317525782
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2500538188
/workspace/coverage/default/8.sram_ctrl_ram_cfg.35007245
/workspace/coverage/default/8.sram_ctrl_regwen.2375581052
/workspace/coverage/default/8.sram_ctrl_smoke.211651750
/workspace/coverage/default/8.sram_ctrl_stress_all.3776234332
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2392216573
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1136346298
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.370067101
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1971751591
/workspace/coverage/default/9.sram_ctrl_alert_test.3548598832
/workspace/coverage/default/9.sram_ctrl_bijection.3630537506
/workspace/coverage/default/9.sram_ctrl_executable.16650817
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3313112823
/workspace/coverage/default/9.sram_ctrl_max_throughput.203909065
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1026899348
/workspace/coverage/default/9.sram_ctrl_mem_walk.3682916240
/workspace/coverage/default/9.sram_ctrl_multiple_keys.2559786777
/workspace/coverage/default/9.sram_ctrl_partial_access.4202830154
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.947526272
/workspace/coverage/default/9.sram_ctrl_ram_cfg.307119651
/workspace/coverage/default/9.sram_ctrl_regwen.4167625984
/workspace/coverage/default/9.sram_ctrl_smoke.850696964
/workspace/coverage/default/9.sram_ctrl_stress_all.752481756
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2328813698
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.3037728313
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3492093132



Total test records in report: 1023
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/4.sram_ctrl_alert_test.1007278326 Apr 28 03:39:34 PM PDT 24 Apr 28 03:39:36 PM PDT 24 15106861 ps
T2 /workspace/coverage/default/17.sram_ctrl_partial_access.568681598 Apr 28 03:40:24 PM PDT 24 Apr 28 03:40:29 PM PDT 24 480598352 ps
T3 /workspace/coverage/default/7.sram_ctrl_regwen.4052993855 Apr 28 03:39:48 PM PDT 24 Apr 28 03:53:00 PM PDT 24 10447425269 ps
T11 /workspace/coverage/default/47.sram_ctrl_alert_test.2238517771 Apr 28 03:42:49 PM PDT 24 Apr 28 03:42:50 PM PDT 24 40399147 ps
T4 /workspace/coverage/default/30.sram_ctrl_multiple_keys.1340371857 Apr 28 03:41:03 PM PDT 24 Apr 28 04:24:12 PM PDT 24 19114033467 ps
T5 /workspace/coverage/default/20.sram_ctrl_mem_partial_access.1120066726 Apr 28 03:40:34 PM PDT 24 Apr 28 03:40:37 PM PDT 24 344698399 ps
T6 /workspace/coverage/default/41.sram_ctrl_smoke.1080631592 Apr 28 03:42:02 PM PDT 24 Apr 28 03:42:14 PM PDT 24 1535210409 ps
T12 /workspace/coverage/default/10.sram_ctrl_access_during_key_req.3028999982 Apr 28 03:39:52 PM PDT 24 Apr 28 03:50:40 PM PDT 24 1637963613 ps
T13 /workspace/coverage/default/2.sram_ctrl_max_throughput.316718192 Apr 28 03:39:25 PM PDT 24 Apr 28 03:40:18 PM PDT 24 102674052 ps
T14 /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.2054134391 Apr 28 03:41:43 PM PDT 24 Apr 28 03:42:28 PM PDT 24 121028074 ps
T15 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3096139240 Apr 28 03:39:58 PM PDT 24 Apr 28 03:44:01 PM PDT 24 10116594085 ps
T16 /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.33163709 Apr 28 03:43:05 PM PDT 24 Apr 28 03:58:42 PM PDT 24 8524104740 ps
T17 /workspace/coverage/default/4.sram_ctrl_access_during_key_req.1971281159 Apr 28 03:39:34 PM PDT 24 Apr 28 03:48:49 PM PDT 24 1281539995 ps
T21 /workspace/coverage/default/14.sram_ctrl_alert_test.3982195922 Apr 28 03:40:08 PM PDT 24 Apr 28 03:40:10 PM PDT 24 48344234 ps
T48 /workspace/coverage/default/12.sram_ctrl_max_throughput.627578710 Apr 28 03:39:57 PM PDT 24 Apr 28 03:40:03 PM PDT 24 55981937 ps
T18 /workspace/coverage/default/33.sram_ctrl_regwen.1678096551 Apr 28 03:41:22 PM PDT 24 Apr 28 04:01:51 PM PDT 24 2188058116 ps
T49 /workspace/coverage/default/6.sram_ctrl_max_throughput.3128561176 Apr 28 03:39:44 PM PDT 24 Apr 28 03:41:36 PM PDT 24 1186709836 ps
T23 /workspace/coverage/default/13.sram_ctrl_stress_all.440618636 Apr 28 03:40:02 PM PDT 24 Apr 28 05:13:43 PM PDT 24 51372154740 ps
T24 /workspace/coverage/default/45.sram_ctrl_regwen.4127748975 Apr 28 03:42:40 PM PDT 24 Apr 28 04:03:59 PM PDT 24 34719820722 ps
T39 /workspace/coverage/default/46.sram_ctrl_regwen.992505417 Apr 28 03:42:42 PM PDT 24 Apr 28 04:15:47 PM PDT 24 20843102199 ps
T50 /workspace/coverage/default/11.sram_ctrl_stress_pipeline.1446202491 Apr 28 03:40:00 PM PDT 24 Apr 28 03:43:02 PM PDT 24 7389826979 ps
T7 /workspace/coverage/default/29.sram_ctrl_lc_escalation.1502208927 Apr 28 03:41:01 PM PDT 24 Apr 28 03:41:08 PM PDT 24 500391704 ps
T27 /workspace/coverage/default/39.sram_ctrl_ram_cfg.192024324 Apr 28 03:41:58 PM PDT 24 Apr 28 03:41:59 PM PDT 24 211967710 ps
T139 /workspace/coverage/default/43.sram_ctrl_mem_walk.123919145 Apr 28 03:42:19 PM PDT 24 Apr 28 03:42:25 PM PDT 24 339496594 ps
T119 /workspace/coverage/default/14.sram_ctrl_executable.1997117936 Apr 28 03:40:07 PM PDT 24 Apr 28 03:44:09 PM PDT 24 6551731420 ps
T131 /workspace/coverage/default/43.sram_ctrl_smoke.2673864188 Apr 28 03:42:16 PM PDT 24 Apr 28 03:44:17 PM PDT 24 132952870 ps
T10 /workspace/coverage/default/2.sram_ctrl_sec_cm.2131642198 Apr 28 03:39:38 PM PDT 24 Apr 28 03:39:40 PM PDT 24 559241925 ps
T32 /workspace/coverage/default/3.sram_ctrl_mem_partial_access.1293958851 Apr 28 03:39:41 PM PDT 24 Apr 28 03:39:46 PM PDT 24 95521614 ps
T33 /workspace/coverage/default/8.sram_ctrl_max_throughput.969785999 Apr 28 03:39:53 PM PDT 24 Apr 28 03:41:27 PM PDT 24 1031657200 ps
T28 /workspace/coverage/default/22.sram_ctrl_ram_cfg.1121024532 Apr 28 03:40:35 PM PDT 24 Apr 28 03:40:36 PM PDT 24 42877413 ps
T34 /workspace/coverage/default/47.sram_ctrl_access_during_key_req.2819928810 Apr 28 03:42:46 PM PDT 24 Apr 28 04:11:06 PM PDT 24 44206260213 ps
T22 /workspace/coverage/default/22.sram_ctrl_alert_test.3971943454 Apr 28 03:40:38 PM PDT 24 Apr 28 03:40:40 PM PDT 24 36693980 ps
T35 /workspace/coverage/default/11.sram_ctrl_max_throughput.1385730974 Apr 28 03:40:00 PM PDT 24 Apr 28 03:41:19 PM PDT 24 192476126 ps
T36 /workspace/coverage/default/28.sram_ctrl_mem_walk.1672974952 Apr 28 03:40:54 PM PDT 24 Apr 28 03:41:05 PM PDT 24 1354531344 ps
T37 /workspace/coverage/default/10.sram_ctrl_regwen.1776157802 Apr 28 03:39:54 PM PDT 24 Apr 28 03:58:59 PM PDT 24 12217361587 ps
T38 /workspace/coverage/default/6.sram_ctrl_mem_walk.1103075130 Apr 28 03:39:44 PM PDT 24 Apr 28 03:39:55 PM PDT 24 695665442 ps
T64 /workspace/coverage/default/0.sram_ctrl_access_during_key_req.3693567948 Apr 28 03:39:21 PM PDT 24 Apr 28 03:44:47 PM PDT 24 18234015118 ps
T29 /workspace/coverage/default/1.sram_ctrl_ram_cfg.808043801 Apr 28 03:39:31 PM PDT 24 Apr 28 03:39:33 PM PDT 24 95482152 ps
T140 /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3818244030 Apr 28 03:42:20 PM PDT 24 Apr 28 03:42:22 PM PDT 24 39298962 ps
T79 /workspace/coverage/default/42.sram_ctrl_stress_pipeline.1956000637 Apr 28 03:42:11 PM PDT 24 Apr 28 03:46:16 PM PDT 24 10197929919 ps
T126 /workspace/coverage/default/4.sram_ctrl_bijection.2937459434 Apr 28 03:39:41 PM PDT 24 Apr 28 03:40:52 PM PDT 24 3620014542 ps
T141 /workspace/coverage/default/34.sram_ctrl_mem_walk.3755523170 Apr 28 03:41:32 PM PDT 24 Apr 28 03:41:42 PM PDT 24 446398513 ps
T142 /workspace/coverage/default/5.sram_ctrl_alert_test.2940100821 Apr 28 03:39:39 PM PDT 24 Apr 28 03:39:41 PM PDT 24 48797959 ps
T8 /workspace/coverage/default/17.sram_ctrl_lc_escalation.3667165685 Apr 28 03:40:14 PM PDT 24 Apr 28 03:40:18 PM PDT 24 936574018 ps
T123 /workspace/coverage/default/14.sram_ctrl_smoke.1645637709 Apr 28 03:40:05 PM PDT 24 Apr 28 03:40:17 PM PDT 24 443051457 ps
T65 /workspace/coverage/default/37.sram_ctrl_access_during_key_req.3253144180 Apr 28 03:41:45 PM PDT 24 Apr 28 03:41:59 PM PDT 24 389881066 ps
T143 /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.1273025675 Apr 28 03:40:27 PM PDT 24 Apr 28 03:41:29 PM PDT 24 118232037 ps
T66 /workspace/coverage/default/19.sram_ctrl_access_during_key_req.3489620222 Apr 28 03:40:24 PM PDT 24 Apr 28 04:05:51 PM PDT 24 8046597784 ps
T120 /workspace/coverage/default/9.sram_ctrl_executable.16650817 Apr 28 03:39:48 PM PDT 24 Apr 28 03:59:28 PM PDT 24 37318460923 ps
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T145 /workspace/coverage/default/23.sram_ctrl_ram_cfg.3646267795 Apr 28 03:40:41 PM PDT 24 Apr 28 03:40:42 PM PDT 24 52205587 ps
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T146 /workspace/coverage/default/4.sram_ctrl_max_throughput.3094169402 Apr 28 03:39:39 PM PDT 24 Apr 28 03:40:52 PM PDT 24 113516430 ps
T80 /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1174633104 Apr 28 03:43:00 PM PDT 24 Apr 28 03:48:13 PM PDT 24 22547280089 ps
T147 /workspace/coverage/default/36.sram_ctrl_max_throughput.1477924032 Apr 28 03:41:37 PM PDT 24 Apr 28 03:41:45 PM PDT 24 217163245 ps
T148 /workspace/coverage/default/17.sram_ctrl_bijection.2708193937 Apr 28 03:40:09 PM PDT 24 Apr 28 03:40:30 PM PDT 24 2327361640 ps
T51 /workspace/coverage/default/38.sram_ctrl_regwen.1985661783 Apr 28 03:41:53 PM PDT 24 Apr 28 04:06:40 PM PDT 24 20407213743 ps
T149 /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.2638021610 Apr 28 03:39:38 PM PDT 24 Apr 28 03:41:45 PM PDT 24 296539454 ps
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T150 /workspace/coverage/default/21.sram_ctrl_multiple_keys.3859551684 Apr 28 03:40:35 PM PDT 24 Apr 28 03:43:30 PM PDT 24 3753907734 ps
T151 /workspace/coverage/default/41.sram_ctrl_bijection.2727038918 Apr 28 03:42:06 PM PDT 24 Apr 28 03:42:34 PM PDT 24 1836817974 ps
T107 /workspace/coverage/default/14.sram_ctrl_stress_all.1705402565 Apr 28 03:40:08 PM PDT 24 Apr 28 04:12:39 PM PDT 24 49929613394 ps
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T67 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.16037586 Apr 28 03:41:57 PM PDT 24 Apr 28 03:42:01 PM PDT 24 389691431 ps
T68 /workspace/coverage/default/5.sram_ctrl_access_during_key_req.800769806 Apr 28 03:39:40 PM PDT 24 Apr 28 03:45:47 PM PDT 24 2497129299 ps
T152 /workspace/coverage/default/22.sram_ctrl_partial_access.3793352851 Apr 28 03:40:34 PM PDT 24 Apr 28 03:40:44 PM PDT 24 392651715 ps
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T155 /workspace/coverage/default/5.sram_ctrl_multiple_keys.693715009 Apr 28 03:39:34 PM PDT 24 Apr 28 04:03:59 PM PDT 24 16511222014 ps
T82 /workspace/coverage/default/25.sram_ctrl_mem_partial_access.2852342440 Apr 28 03:40:44 PM PDT 24 Apr 28 03:40:49 PM PDT 24 436503852 ps
T133 /workspace/coverage/default/13.sram_ctrl_multiple_keys.4228682023 Apr 28 03:39:59 PM PDT 24 Apr 28 03:42:09 PM PDT 24 1096834805 ps
T156 /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3873431552 Apr 28 03:42:17 PM PDT 24 Apr 28 03:44:14 PM PDT 24 335825264 ps
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T138 /workspace/coverage/default/45.sram_ctrl_access_during_key_req.3443297998 Apr 28 03:42:33 PM PDT 24 Apr 28 03:55:40 PM PDT 24 1591201591 ps
T157 /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.3506772445 Apr 28 03:40:16 PM PDT 24 Apr 28 03:40:20 PM PDT 24 210176731 ps
T158 /workspace/coverage/default/28.sram_ctrl_ram_cfg.685496198 Apr 28 03:40:56 PM PDT 24 Apr 28 03:40:59 PM PDT 24 84427405 ps
T159 /workspace/coverage/default/26.sram_ctrl_max_throughput.1807593123 Apr 28 03:40:46 PM PDT 24 Apr 28 03:40:49 PM PDT 24 75083284 ps
T83 /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2470001196 Apr 28 03:42:50 PM PDT 24 Apr 28 03:52:51 PM PDT 24 82356957588 ps
T160 /workspace/coverage/default/34.sram_ctrl_ram_cfg.650087025 Apr 28 03:41:32 PM PDT 24 Apr 28 03:41:33 PM PDT 24 29114197 ps
T128 /workspace/coverage/default/17.sram_ctrl_smoke.582766317 Apr 28 03:40:13 PM PDT 24 Apr 28 03:40:16 PM PDT 24 197357469 ps
T84 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.3513317265 Apr 28 03:40:37 PM PDT 24 Apr 28 03:48:05 PM PDT 24 9021494676 ps
T85 /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.1021028755 Apr 28 03:40:43 PM PDT 24 Apr 28 03:48:52 PM PDT 24 101959473447 ps
T122 /workspace/coverage/default/40.sram_ctrl_regwen.400077194 Apr 28 03:42:05 PM PDT 24 Apr 28 03:57:51 PM PDT 24 7964044395 ps
T161 /workspace/coverage/default/35.sram_ctrl_partial_access.3240164133 Apr 28 03:41:34 PM PDT 24 Apr 28 03:43:21 PM PDT 24 198559479 ps
T162 /workspace/coverage/default/20.sram_ctrl_mem_walk.1554117219 Apr 28 03:40:27 PM PDT 24 Apr 28 03:40:39 PM PDT 24 2698210212 ps
T163 /workspace/coverage/default/29.sram_ctrl_regwen.3973443941 Apr 28 03:41:00 PM PDT 24 Apr 28 03:46:56 PM PDT 24 9449568292 ps
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T165 /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2710907625 Apr 28 03:41:43 PM PDT 24 Apr 28 03:49:18 PM PDT 24 12940815088 ps
T166 /workspace/coverage/default/13.sram_ctrl_stress_pipeline.962295446 Apr 28 03:39:57 PM PDT 24 Apr 28 03:43:57 PM PDT 24 4899378324 ps
T137 /workspace/coverage/default/42.sram_ctrl_lc_escalation.2624385870 Apr 28 03:42:18 PM PDT 24 Apr 28 03:42:22 PM PDT 24 999462349 ps
T167 /workspace/coverage/default/19.sram_ctrl_smoke.3556066453 Apr 28 03:40:22 PM PDT 24 Apr 28 03:42:21 PM PDT 24 4839662320 ps
T25 /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3969722194 Apr 28 03:41:12 PM PDT 24 Apr 28 03:49:57 PM PDT 24 7327590125 ps
T168 /workspace/coverage/default/38.sram_ctrl_partial_access.4100614555 Apr 28 03:41:54 PM PDT 24 Apr 28 03:42:06 PM PDT 24 886923582 ps
T121 /workspace/coverage/default/24.sram_ctrl_stress_all.2204728980 Apr 28 03:40:43 PM PDT 24 Apr 28 04:42:12 PM PDT 24 41194890586 ps
T169 /workspace/coverage/default/41.sram_ctrl_regwen.3756278233 Apr 28 03:42:05 PM PDT 24 Apr 28 03:43:45 PM PDT 24 6806372823 ps
T170 /workspace/coverage/default/26.sram_ctrl_ram_cfg.1618330917 Apr 28 03:40:50 PM PDT 24 Apr 28 03:40:51 PM PDT 24 28060549 ps
T171 /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2927299779 Apr 28 03:39:18 PM PDT 24 Apr 28 03:43:57 PM PDT 24 9547127808 ps
T172 /workspace/coverage/default/6.sram_ctrl_alert_test.3747189471 Apr 28 03:39:46 PM PDT 24 Apr 28 03:39:47 PM PDT 24 15471648 ps
T173 /workspace/coverage/default/41.sram_ctrl_max_throughput.344389769 Apr 28 03:42:08 PM PDT 24 Apr 28 03:42:28 PM PDT 24 136730359 ps
T174 /workspace/coverage/default/22.sram_ctrl_access_during_key_req.1556623011 Apr 28 03:40:37 PM PDT 24 Apr 28 04:16:20 PM PDT 24 3825420905 ps
T175 /workspace/coverage/default/0.sram_ctrl_alert_test.3447352739 Apr 28 03:39:20 PM PDT 24 Apr 28 03:39:22 PM PDT 24 14319950 ps
T176 /workspace/coverage/default/11.sram_ctrl_mem_walk.2650126076 Apr 28 03:39:53 PM PDT 24 Apr 28 03:40:04 PM PDT 24 435889617 ps
T177 /workspace/coverage/default/30.sram_ctrl_max_throughput.3841798367 Apr 28 03:41:09 PM PDT 24 Apr 28 03:42:54 PM PDT 24 131783825 ps
T136 /workspace/coverage/default/28.sram_ctrl_multiple_keys.4081698081 Apr 28 03:40:56 PM PDT 24 Apr 28 04:00:52 PM PDT 24 8936921354 ps
T178 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.3763260261 Apr 28 03:40:44 PM PDT 24 Apr 28 03:46:44 PM PDT 24 13584126692 ps
T179 /workspace/coverage/default/29.sram_ctrl_multiple_keys.2416257431 Apr 28 03:40:57 PM PDT 24 Apr 28 03:51:10 PM PDT 24 6667209890 ps
T180 /workspace/coverage/default/5.sram_ctrl_max_throughput.4131740222 Apr 28 03:39:34 PM PDT 24 Apr 28 03:40:26 PM PDT 24 437969730 ps
T181 /workspace/coverage/default/34.sram_ctrl_max_throughput.1185785187 Apr 28 03:41:26 PM PDT 24 Apr 28 03:42:37 PM PDT 24 436894460 ps
T182 /workspace/coverage/default/30.sram_ctrl_alert_test.1810899930 Apr 28 03:41:20 PM PDT 24 Apr 28 03:41:21 PM PDT 24 34112351 ps
T26 /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3399341147 Apr 28 03:41:24 PM PDT 24 Apr 28 03:46:45 PM PDT 24 821844279 ps
T183 /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.1979109595 Apr 28 03:40:12 PM PDT 24 Apr 28 03:40:39 PM PDT 24 335527830 ps
T184 /workspace/coverage/default/48.sram_ctrl_partial_access.1021767228 Apr 28 03:42:51 PM PDT 24 Apr 28 03:43:08 PM PDT 24 3332188638 ps
T185 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.3028028464 Apr 28 03:40:44 PM PDT 24 Apr 28 03:40:49 PM PDT 24 219707497 ps
T19 /workspace/coverage/default/4.sram_ctrl_sec_cm.838138885 Apr 28 03:39:38 PM PDT 24 Apr 28 03:39:41 PM PDT 24 555906533 ps
T186 /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3992209860 Apr 28 03:39:24 PM PDT 24 Apr 28 03:43:48 PM PDT 24 45858389338 ps
T187 /workspace/coverage/default/38.sram_ctrl_smoke.2853528074 Apr 28 03:41:50 PM PDT 24 Apr 28 03:42:05 PM PDT 24 62267361 ps
T188 /workspace/coverage/default/0.sram_ctrl_multiple_keys.2908371738 Apr 28 03:39:21 PM PDT 24 Apr 28 03:39:54 PM PDT 24 557346557 ps
T189 /workspace/coverage/default/5.sram_ctrl_bijection.3165240712 Apr 28 03:39:34 PM PDT 24 Apr 28 03:39:58 PM PDT 24 2464751708 ps
T190 /workspace/coverage/default/9.sram_ctrl_access_during_key_req.1971751591 Apr 28 03:39:47 PM PDT 24 Apr 28 03:48:51 PM PDT 24 1775346817 ps
T191 /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3686181313 Apr 28 03:39:34 PM PDT 24 Apr 28 03:46:32 PM PDT 24 19600190217 ps
T192 /workspace/coverage/default/10.sram_ctrl_stress_pipeline.76827263 Apr 28 03:39:47 PM PDT 24 Apr 28 03:44:12 PM PDT 24 5703312685 ps
T193 /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.391958597 Apr 28 03:39:54 PM PDT 24 Apr 28 03:40:50 PM PDT 24 191604115 ps
T194 /workspace/coverage/default/15.sram_ctrl_bijection.3053887643 Apr 28 03:40:08 PM PDT 24 Apr 28 03:41:27 PM PDT 24 5137484194 ps
T195 /workspace/coverage/default/5.sram_ctrl_mem_walk.3701986331 Apr 28 03:39:39 PM PDT 24 Apr 28 03:39:46 PM PDT 24 2851245564 ps
T196 /workspace/coverage/default/12.sram_ctrl_ram_cfg.2869850332 Apr 28 03:39:56 PM PDT 24 Apr 28 03:39:58 PM PDT 24 28018502 ps
T197 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.3350478892 Apr 28 03:41:34 PM PDT 24 Apr 28 03:55:19 PM PDT 24 5351930879 ps
T198 /workspace/coverage/default/16.sram_ctrl_stress_all.4281068618 Apr 28 03:40:12 PM PDT 24 Apr 28 04:04:29 PM PDT 24 4889156172 ps
T199 /workspace/coverage/default/15.sram_ctrl_lc_escalation.2962060675 Apr 28 03:40:15 PM PDT 24 Apr 28 03:40:19 PM PDT 24 2893898424 ps
T41 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3589616441 Apr 28 03:40:28 PM PDT 24 Apr 28 03:55:52 PM PDT 24 4041152309 ps
T200 /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3737682713 Apr 28 03:41:08 PM PDT 24 Apr 28 03:47:43 PM PDT 24 14748065830 ps
T124 /workspace/coverage/default/46.sram_ctrl_stress_all.1429160124 Apr 28 03:42:47 PM PDT 24 Apr 28 04:27:35 PM PDT 24 12760276349 ps
T201 /workspace/coverage/default/43.sram_ctrl_executable.2330591579 Apr 28 03:42:18 PM PDT 24 Apr 28 04:04:10 PM PDT 24 30383143588 ps
T202 /workspace/coverage/default/8.sram_ctrl_executable.2679490935 Apr 28 03:39:46 PM PDT 24 Apr 28 03:45:55 PM PDT 24 2841681641 ps
T203 /workspace/coverage/default/49.sram_ctrl_stress_all.10826324 Apr 28 03:43:05 PM PDT 24 Apr 28 04:05:53 PM PDT 24 82632284626 ps
T204 /workspace/coverage/default/14.sram_ctrl_regwen.285412482 Apr 28 03:40:06 PM PDT 24 Apr 28 04:02:48 PM PDT 24 2088782698 ps
T205 /workspace/coverage/default/11.sram_ctrl_partial_access.4028251271 Apr 28 03:39:54 PM PDT 24 Apr 28 03:40:18 PM PDT 24 4313541337 ps
T206 /workspace/coverage/default/43.sram_ctrl_access_during_key_req.3674185622 Apr 28 03:42:20 PM PDT 24 Apr 28 03:59:02 PM PDT 24 9335543257 ps
T207 /workspace/coverage/default/18.sram_ctrl_bijection.3803792861 Apr 28 03:40:16 PM PDT 24 Apr 28 03:40:57 PM PDT 24 658286048 ps
T208 /workspace/coverage/default/45.sram_ctrl_bijection.2889017800 Apr 28 03:42:35 PM PDT 24 Apr 28 03:43:19 PM PDT 24 2635471841 ps
T209 /workspace/coverage/default/4.sram_ctrl_lc_escalation.1384767549 Apr 28 03:39:32 PM PDT 24 Apr 28 03:39:35 PM PDT 24 983547001 ps
T210 /workspace/coverage/default/33.sram_ctrl_access_during_key_req.407985869 Apr 28 03:41:21 PM PDT 24 Apr 28 04:20:56 PM PDT 24 3653603710 ps
T211 /workspace/coverage/default/4.sram_ctrl_partial_access.4217911649 Apr 28 03:39:35 PM PDT 24 Apr 28 03:42:03 PM PDT 24 2807919210 ps
T212 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2527439138 Apr 28 03:41:54 PM PDT 24 Apr 28 03:46:51 PM PDT 24 4132863034 ps
T42 /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1468131786 Apr 28 03:42:00 PM PDT 24 Apr 28 03:49:32 PM PDT 24 1998211697 ps
T213 /workspace/coverage/default/9.sram_ctrl_partial_access.4202830154 Apr 28 03:39:49 PM PDT 24 Apr 28 03:39:57 PM PDT 24 877970368 ps
T214 /workspace/coverage/default/24.sram_ctrl_multiple_keys.2131438362 Apr 28 03:40:37 PM PDT 24 Apr 28 04:02:16 PM PDT 24 57992504758 ps
T215 /workspace/coverage/default/10.sram_ctrl_multiple_keys.2931873580 Apr 28 03:39:49 PM PDT 24 Apr 28 04:01:11 PM PDT 24 54910398736 ps
T216 /workspace/coverage/default/46.sram_ctrl_bijection.635716347 Apr 28 03:42:40 PM PDT 24 Apr 28 03:43:42 PM PDT 24 3531016899 ps
T217 /workspace/coverage/default/28.sram_ctrl_stress_all.945300702 Apr 28 03:40:57 PM PDT 24 Apr 28 03:45:16 PM PDT 24 1440578868 ps
T218 /workspace/coverage/default/4.sram_ctrl_stress_all.4087594143 Apr 28 03:39:35 PM PDT 24 Apr 28 04:32:28 PM PDT 24 55874497894 ps
T219 /workspace/coverage/default/8.sram_ctrl_bijection.2706478658 Apr 28 03:40:02 PM PDT 24 Apr 28 03:41:21 PM PDT 24 8290212793 ps
T220 /workspace/coverage/default/47.sram_ctrl_stress_all.4193157744 Apr 28 03:42:46 PM PDT 24 Apr 28 04:06:01 PM PDT 24 4415528188 ps
T221 /workspace/coverage/default/13.sram_ctrl_max_throughput.84033294 Apr 28 03:40:00 PM PDT 24 Apr 28 03:41:21 PM PDT 24 107519389 ps
T222 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3163268408 Apr 28 03:42:45 PM PDT 24 Apr 28 03:42:50 PM PDT 24 269758611 ps
T223 /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.3164574177 Apr 28 03:42:11 PM PDT 24 Apr 28 03:47:10 PM PDT 24 4228817851 ps
T224 /workspace/coverage/default/1.sram_ctrl_access_during_key_req.502151046 Apr 28 03:39:21 PM PDT 24 Apr 28 03:44:09 PM PDT 24 11754883338 ps
T43 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.56952674 Apr 28 03:39:57 PM PDT 24 Apr 28 03:42:35 PM PDT 24 781356870 ps
T225 /workspace/coverage/default/16.sram_ctrl_max_throughput.2117853143 Apr 28 03:40:12 PM PDT 24 Apr 28 03:41:22 PM PDT 24 492784216 ps
T226 /workspace/coverage/default/36.sram_ctrl_mem_partial_access.3685628645 Apr 28 03:41:40 PM PDT 24 Apr 28 03:41:43 PM PDT 24 47509007 ps
T227 /workspace/coverage/default/9.sram_ctrl_stress_all.752481756 Apr 28 03:39:54 PM PDT 24 Apr 28 04:18:46 PM PDT 24 56003677185 ps
T228 /workspace/coverage/default/26.sram_ctrl_smoke.2672085468 Apr 28 03:40:46 PM PDT 24 Apr 28 03:41:07 PM PDT 24 2003504971 ps
T229 /workspace/coverage/default/1.sram_ctrl_regwen.2799060766 Apr 28 03:39:21 PM PDT 24 Apr 28 04:06:48 PM PDT 24 3825501031 ps
T230 /workspace/coverage/default/41.sram_ctrl_executable.1052123799 Apr 28 03:42:11 PM PDT 24 Apr 28 04:10:52 PM PDT 24 16827257832 ps
T231 /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.694988930 Apr 28 03:39:32 PM PDT 24 Apr 28 03:44:10 PM PDT 24 4036959865 ps
T232 /workspace/coverage/default/49.sram_ctrl_partial_access.2750570836 Apr 28 03:43:00 PM PDT 24 Apr 28 03:44:30 PM PDT 24 2071518163 ps
T233 /workspace/coverage/default/8.sram_ctrl_lc_escalation.4293002214 Apr 28 03:40:01 PM PDT 24 Apr 28 03:40:09 PM PDT 24 773372688 ps
T234 /workspace/coverage/default/40.sram_ctrl_ram_cfg.3754045854 Apr 28 03:42:03 PM PDT 24 Apr 28 03:42:04 PM PDT 24 44005072 ps
T235 /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.1376101054 Apr 28 03:40:37 PM PDT 24 Apr 28 03:41:55 PM PDT 24 498532923 ps
T236 /workspace/coverage/default/2.sram_ctrl_executable.1661782713 Apr 28 03:39:25 PM PDT 24 Apr 28 04:05:22 PM PDT 24 169465910870 ps
T237 /workspace/coverage/default/35.sram_ctrl_ram_cfg.295844833 Apr 28 03:41:37 PM PDT 24 Apr 28 03:41:38 PM PDT 24 33148262 ps
T44 /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.95236712 Apr 28 03:42:18 PM PDT 24 Apr 28 03:42:25 PM PDT 24 733133912 ps
T238 /workspace/coverage/default/37.sram_ctrl_executable.3405320277 Apr 28 03:41:49 PM PDT 24 Apr 28 04:00:23 PM PDT 24 4182694405 ps
T239 /workspace/coverage/default/4.sram_ctrl_multiple_keys.2140565898 Apr 28 03:39:30 PM PDT 24 Apr 28 04:00:23 PM PDT 24 7366617210 ps
T240 /workspace/coverage/default/8.sram_ctrl_partial_access.3317525782 Apr 28 03:40:02 PM PDT 24 Apr 28 03:40:17 PM PDT 24 275940256 ps
T241 /workspace/coverage/default/6.sram_ctrl_stress_all.2909950325 Apr 28 03:39:56 PM PDT 24 Apr 28 03:46:39 PM PDT 24 4724262069 ps
T242 /workspace/coverage/default/24.sram_ctrl_mem_partial_access.4230468494 Apr 28 03:40:41 PM PDT 24 Apr 28 03:40:46 PM PDT 24 222839793 ps
T243 /workspace/coverage/default/31.sram_ctrl_regwen.3493586149 Apr 28 03:41:16 PM PDT 24 Apr 28 03:41:42 PM PDT 24 319302383 ps
T244 /workspace/coverage/default/14.sram_ctrl_bijection.1266349209 Apr 28 03:40:02 PM PDT 24 Apr 28 03:41:12 PM PDT 24 29872904732 ps
T245 /workspace/coverage/default/49.sram_ctrl_multiple_keys.202393670 Apr 28 03:42:57 PM PDT 24 Apr 28 03:50:34 PM PDT 24 1818081850 ps
T246 /workspace/coverage/default/41.sram_ctrl_lc_escalation.2419601 Apr 28 03:42:05 PM PDT 24 Apr 28 03:42:13 PM PDT 24 1300227438 ps
T247 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.3764111613 Apr 28 03:41:58 PM PDT 24 Apr 28 04:01:11 PM PDT 24 2951585565 ps
T248 /workspace/coverage/default/24.sram_ctrl_partial_access.1099785783 Apr 28 03:40:40 PM PDT 24 Apr 28 03:40:48 PM PDT 24 401108277 ps
T249 /workspace/coverage/default/36.sram_ctrl_multiple_keys.1900669977 Apr 28 03:41:36 PM PDT 24 Apr 28 03:57:25 PM PDT 24 25015831102 ps
T69 /workspace/coverage/default/29.sram_ctrl_mem_partial_access.761535758 Apr 28 03:41:04 PM PDT 24 Apr 28 03:41:08 PM PDT 24 91756831 ps
T250 /workspace/coverage/default/14.sram_ctrl_max_throughput.393275750 Apr 28 03:40:08 PM PDT 24 Apr 28 03:41:25 PM PDT 24 434505730 ps
T251 /workspace/coverage/default/16.sram_ctrl_alert_test.3120957229 Apr 28 03:40:13 PM PDT 24 Apr 28 03:40:14 PM PDT 24 24258849 ps
T252 /workspace/coverage/default/17.sram_ctrl_executable.1384573244 Apr 28 03:40:25 PM PDT 24 Apr 28 03:53:51 PM PDT 24 42807675625 ps
T253 /workspace/coverage/default/38.sram_ctrl_mem_walk.3505824596 Apr 28 03:41:56 PM PDT 24 Apr 28 03:42:08 PM PDT 24 7305139739 ps
T254 /workspace/coverage/default/12.sram_ctrl_stress_all.3278866277 Apr 28 03:40:01 PM PDT 24 Apr 28 04:29:39 PM PDT 24 78945402471 ps
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T70 /workspace/coverage/default/45.sram_ctrl_mem_partial_access.2032199739 Apr 28 03:42:39 PM PDT 24 Apr 28 03:42:44 PM PDT 24 67588784 ps
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T296 /workspace/coverage/default/13.sram_ctrl_partial_access.1901784053 Apr 28 03:39:58 PM PDT 24 Apr 28 03:40:09 PM PDT 24 670212583 ps
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