Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	44442744	1			T2	281		T3	54429		T4	222650
triple_byte_access	2636097	1			T2	274		T3	1165		T4	4352
halfword_access	3955361	1			T2	344		T3	1627		T4	6698
byte_access	5278277	1			T2	501		T3	2136		T4	8674
zero_access	1329065	1			T2	138		T3	551		T4	2201

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28774859

1

T2

768

T3

30042

T4

122015

auto[1]

28866685

1

T2

770

T3

29866

T4

122560

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22177350	1			T2	140		T3	27318		T4	111160
auto[0]	triple_byte_access	1315183	1			T2	135		T3	565		T4	2177
auto[0]	halfword_access	1975784	1			T2	175		T3	814		T4	3259
auto[0]	byte_access	2638552	1			T2	249		T3	1062		T4	4313
auto[0]	zero_access	667990	1			T2	69		T3	283		T4	1106
auto[1]	word_access	22265394	1			T2	141		T3	27111		T4	111490
auto[1]	triple_byte_access	1320914	1			T2	139		T3	600		T4	2175
auto[1]	halfword_access	1979577	1			T2	169		T3	813		T4	3439
auto[1]	byte_access	2639725	1			T2	252		T3	1074		T4	4361
auto[1]	zero_access	661075	1			T2	69		T3	268		T4	1095