Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	140206256	1			T1	255454		T2	161493		T3	6164
instr_valid_dis	110019871	1			T1	255454		T2	862482		T3	6164
instr_en	20934461	1			T2	541634		T11	242268		T29	134398

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10307858	1			T2	164974		T11	34550		T29	140172
sram_ifetch_valid_disable	109431682	1			T1	255454		T2	807184		T3	6164
sram_ifetch_enable	20466716	1			T2	642778		T11	43872		T29	63296

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	140206256	1			T1	255454		T2	161493		T3	6164
hw_debug_en_valid_off	109447044	1			T1	255454		T2	593524		T3	6164
hw_debug_en_on	20384290	1			T2	556050		T11	167174		T29	208948

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	109431682	1			T1	255454		T2	807184		T3	6164
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	96434366	1			T1	255454		T2	529468		T3	6164
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9254208	1			T2	186738		T11	163846		T29	23126
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4717840	1			T2	33524		T11	22414		T29	21610
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1899006	1			T2	18220		T30	61400		T23	82326
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1719136	1			T2	15304		T11	22414		T29	21610
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3922242	1			T2	95184		T11	12136		T29	105354
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1478200	1			T2	22514		T30	17444		T75	56676
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1741744	1			T2	72670		T11	12136		T29	71986
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8123185	1			T2	227260		T11	149734		T29	70814
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3572665	1			T2	104874		T29	59660		T23	7652
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3485758	1			T2	97532		T11	149734		T29	11154

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	7517217	1			T2	266922		T11	43872		T29	17676
lc_exec_en	8338863	1			T2	233606		T11	5304		T29	32780
valid_exec_dis	105790678	1			T1	255454		T2	621824		T3	6164
invalid_exec_dis	30774574	1			T2	807752		T11	78422		T29	203468