Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.08 99.81 96.99 100.00 100.00 98.57 99.70 98.52


Total tests in report: 1022
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
84.98 84.98 97.66 97.66 81.56 81.56 93.63 93.63 100.00 100.00 92.80 92.80 94.90 94.90 34.32 34.32 /workspace/coverage/default/9.sram_ctrl_lc_escalation.1948335003
91.82 6.84 98.25 0.58 87.40 5.84 94.96 1.32 100.00 0.00 94.81 2.02 96.25 1.35 71.06 36.73 /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.607441604
95.36 3.54 99.03 0.78 90.65 3.25 96.42 1.47 100.00 0.00 96.83 2.02 96.25 0.00 88.31 17.25 /workspace/coverage/default/15.sram_ctrl_stress_all.1225155861
96.44 1.08 99.22 0.19 91.56 0.91 96.64 0.21 100.00 0.00 97.69 0.86 96.25 0.00 93.69 5.38 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3939412630
97.06 0.62 99.42 0.19 93.51 1.95 97.00 0.36 100.00 0.00 98.56 0.86 96.85 0.60 94.06 0.37 /workspace/coverage/default/0.sram_ctrl_sec_cm.1958280665
97.57 0.51 99.71 0.29 93.64 0.13 98.78 1.79 100.00 0.00 98.85 0.29 97.00 0.15 94.99 0.93 /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1741041972
97.83 0.26 99.71 0.00 93.64 0.00 98.78 0.00 100.00 0.00 98.85 0.00 97.90 0.90 95.92 0.93 /workspace/coverage/default/31.sram_ctrl_mem_partial_access.728259748
98.03 0.20 99.71 0.00 93.64 0.00 98.86 0.07 100.00 0.00 98.85 0.00 99.25 1.35 95.92 0.00 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3092227722
98.23 0.20 99.71 0.00 94.03 0.39 99.28 0.43 100.00 0.00 98.85 0.00 99.25 0.00 96.47 0.56 /workspace/coverage/default/13.sram_ctrl_alert_test.945902278
98.34 0.12 99.81 0.10 94.03 0.00 100.00 0.72 100.00 0.00 98.85 0.00 99.25 0.00 96.47 0.00 /workspace/coverage/default/12.sram_ctrl_ram_cfg.1837382033
98.45 0.11 99.81 0.00 94.03 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.25 0.00 97.22 0.74 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.686389773
98.54 0.09 99.81 0.00 94.03 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.70 0.45 97.40 0.19 /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2521640684
98.62 0.08 99.81 0.00 94.03 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.70 0.00 97.96 0.56 /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1102157179
98.65 0.03 99.81 0.00 94.03 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.70 0.00 98.14 0.19 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1323916642
98.67 0.03 99.81 0.00 94.03 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.70 0.00 98.33 0.19 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1113997343
98.70 0.03 99.81 0.00 94.03 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.70 0.00 98.52 0.19 /workspace/coverage/default/16.sram_ctrl_executable.1020591363
98.72 0.02 99.81 0.00 94.16 0.13 100.00 0.00 100.00 0.00 98.85 0.00 99.70 0.00 98.52 0.00 /workspace/coverage/default/0.sram_ctrl_access_during_key_req.1042115234

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1353403087
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.4185495328
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.947664535
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1814568638
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3376677228
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1022787023
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1571666761
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1967825609
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2503568731
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3154600656
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2919034426
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1230254854
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.594125480
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1035796108
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1248581389
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3478427574
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3953920718
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.877870298
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.344076247
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1250015536
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3131606832
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1460521314
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3918457405
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1368212475
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.281843247
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.821482427
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3114118714
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1662004620
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3499752540
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1021468139
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2157287122
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3661189142
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3703202721
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.936168982
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2326619493
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.683706061
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.366073349
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3219913972
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1808483921
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1387724270
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3594305760
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1146529565
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1048519521
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2913097747
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4265583317
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1003469721
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.663661337
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2079384327
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.4002612816
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.391454388
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3423022762
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.865744297
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2933010001
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3832774657
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1786559155
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.457448430
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4151536496
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2301587679
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1067129721
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3823144475
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1399161393
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.922328828
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3348450569
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4266538621
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3641170025
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.440782576
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3749785605
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3089563280
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1851270273
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.615299012
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.4003153749
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2956342333
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2868943168
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.524138381
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1109836882
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4154684129
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.153348346
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2012601827
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3485897176
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3644212176
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3109970465
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.901480777
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1411650967
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2509154175
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1137127232
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3009285331
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3739875198
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3904988295
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2058286327
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4197246223
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1390506402
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1488625409
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.699131604
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1777474917
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2548901054
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1985135765
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1853536242
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.4260586369
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3790671056
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.439603366
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3048586625
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.177771118
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1772763727
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.110154793
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1131069278
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2732681331
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.837472662
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3433290763
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3126039993
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.293890609
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.388823808
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2733552686
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.100039591
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.879725240
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.735725652
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3927183275
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3359183451
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.169986625
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.137149487
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3475771621
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1534615467
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2979142561
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1050299417
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1337118174
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.328708113
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3924247650
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1035574059
/workspace/coverage/default/0.sram_ctrl_alert_test.4117168970
/workspace/coverage/default/0.sram_ctrl_bijection.413150862
/workspace/coverage/default/0.sram_ctrl_executable.1232219559
/workspace/coverage/default/0.sram_ctrl_lc_escalation.1052902866
/workspace/coverage/default/0.sram_ctrl_max_throughput.1515208376
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1980703292
/workspace/coverage/default/0.sram_ctrl_mem_walk.3500351916
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3203272649
/workspace/coverage/default/0.sram_ctrl_partial_access.760236234
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3955105103
/workspace/coverage/default/0.sram_ctrl_ram_cfg.2443207823
/workspace/coverage/default/0.sram_ctrl_regwen.1384701027
/workspace/coverage/default/0.sram_ctrl_smoke.3028855411
/workspace/coverage/default/0.sram_ctrl_stress_all.3753648085
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1927395038
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3812057629
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.354136757
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2483878403
/workspace/coverage/default/1.sram_ctrl_alert_test.2640333405
/workspace/coverage/default/1.sram_ctrl_bijection.2220974648
/workspace/coverage/default/1.sram_ctrl_executable.583798472
/workspace/coverage/default/1.sram_ctrl_lc_escalation.1029194813
/workspace/coverage/default/1.sram_ctrl_max_throughput.3273372125
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.271636301
/workspace/coverage/default/1.sram_ctrl_mem_walk.1744370403
/workspace/coverage/default/1.sram_ctrl_multiple_keys.1663868335
/workspace/coverage/default/1.sram_ctrl_partial_access.2666144662
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.824555996
/workspace/coverage/default/1.sram_ctrl_ram_cfg.689183838
/workspace/coverage/default/1.sram_ctrl_regwen.3950051485
/workspace/coverage/default/1.sram_ctrl_sec_cm.3592499673
/workspace/coverage/default/1.sram_ctrl_smoke.100671952
/workspace/coverage/default/1.sram_ctrl_stress_all.2132462404
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.277381297
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1976185835
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.231596182
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2671338736
/workspace/coverage/default/10.sram_ctrl_alert_test.2796492912
/workspace/coverage/default/10.sram_ctrl_bijection.1476012404
/workspace/coverage/default/10.sram_ctrl_executable.1042021750
/workspace/coverage/default/10.sram_ctrl_lc_escalation.1823104502
/workspace/coverage/default/10.sram_ctrl_max_throughput.2863702916
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.1584286846
/workspace/coverage/default/10.sram_ctrl_mem_walk.1968189541
/workspace/coverage/default/10.sram_ctrl_multiple_keys.4082176331
/workspace/coverage/default/10.sram_ctrl_partial_access.2496489919
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.592562488
/workspace/coverage/default/10.sram_ctrl_ram_cfg.3017685160
/workspace/coverage/default/10.sram_ctrl_regwen.2335459211
/workspace/coverage/default/10.sram_ctrl_smoke.2051590452
/workspace/coverage/default/10.sram_ctrl_stress_all.1038363458
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1935142059
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.290842606
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3923912142
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1065233518
/workspace/coverage/default/11.sram_ctrl_alert_test.89759529
/workspace/coverage/default/11.sram_ctrl_bijection.3333050755
/workspace/coverage/default/11.sram_ctrl_executable.3299468861
/workspace/coverage/default/11.sram_ctrl_lc_escalation.2016670393
/workspace/coverage/default/11.sram_ctrl_max_throughput.439815081
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.2638029987
/workspace/coverage/default/11.sram_ctrl_mem_walk.387659999
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3785216613
/workspace/coverage/default/11.sram_ctrl_partial_access.1334545209
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2786126434
/workspace/coverage/default/11.sram_ctrl_regwen.347391029
/workspace/coverage/default/11.sram_ctrl_smoke.3633512922
/workspace/coverage/default/11.sram_ctrl_stress_all.2857547648
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2097588658
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.1627434597
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.783738231
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.272499068
/workspace/coverage/default/12.sram_ctrl_alert_test.3673273547
/workspace/coverage/default/12.sram_ctrl_bijection.1573612032
/workspace/coverage/default/12.sram_ctrl_executable.3872366869
/workspace/coverage/default/12.sram_ctrl_lc_escalation.1519034502
/workspace/coverage/default/12.sram_ctrl_max_throughput.3756353051
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.2135535735
/workspace/coverage/default/12.sram_ctrl_mem_walk.1554207354
/workspace/coverage/default/12.sram_ctrl_multiple_keys.2190750831
/workspace/coverage/default/12.sram_ctrl_partial_access.757483285
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2683589919
/workspace/coverage/default/12.sram_ctrl_regwen.2505411383
/workspace/coverage/default/12.sram_ctrl_smoke.1046847915
/workspace/coverage/default/12.sram_ctrl_stress_all.40099382
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1572348525
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/workspace/coverage/default/43.sram_ctrl_stress_pipeline.1678191942
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3985788756
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.3423840568
/workspace/coverage/default/44.sram_ctrl_alert_test.1615303407
/workspace/coverage/default/44.sram_ctrl_bijection.3254540146
/workspace/coverage/default/44.sram_ctrl_executable.3579352318
/workspace/coverage/default/44.sram_ctrl_lc_escalation.448584160
/workspace/coverage/default/44.sram_ctrl_max_throughput.1073114112
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.1035029062
/workspace/coverage/default/44.sram_ctrl_mem_walk.1293556464
/workspace/coverage/default/44.sram_ctrl_multiple_keys.1058608838
/workspace/coverage/default/44.sram_ctrl_partial_access.2935360362
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1215946570
/workspace/coverage/default/44.sram_ctrl_ram_cfg.2839167350
/workspace/coverage/default/44.sram_ctrl_regwen.3541229099
/workspace/coverage/default/44.sram_ctrl_smoke.3601889845
/workspace/coverage/default/44.sram_ctrl_stress_all.2424033707
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2151119804
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1454265516
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2271165379
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.209343588
/workspace/coverage/default/45.sram_ctrl_alert_test.578341246
/workspace/coverage/default/45.sram_ctrl_bijection.3594872987
/workspace/coverage/default/45.sram_ctrl_executable.756973225
/workspace/coverage/default/45.sram_ctrl_lc_escalation.3149459718
/workspace/coverage/default/45.sram_ctrl_max_throughput.2768088641
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.3336055870
/workspace/coverage/default/45.sram_ctrl_mem_walk.2843318679
/workspace/coverage/default/45.sram_ctrl_multiple_keys.683751437
/workspace/coverage/default/45.sram_ctrl_partial_access.3509789999
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.219700802
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1576536501
/workspace/coverage/default/45.sram_ctrl_regwen.1513631828
/workspace/coverage/default/45.sram_ctrl_smoke.2815110286
/workspace/coverage/default/45.sram_ctrl_stress_all.2406989257
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3689807416
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2938442634
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.997643574
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1679422373
/workspace/coverage/default/46.sram_ctrl_alert_test.2152016367
/workspace/coverage/default/46.sram_ctrl_bijection.1263733195
/workspace/coverage/default/46.sram_ctrl_executable.1664449253
/workspace/coverage/default/46.sram_ctrl_lc_escalation.465077450
/workspace/coverage/default/46.sram_ctrl_max_throughput.1645490603
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.4246077149
/workspace/coverage/default/46.sram_ctrl_mem_walk.2411993449
/workspace/coverage/default/46.sram_ctrl_multiple_keys.1313934206
/workspace/coverage/default/46.sram_ctrl_partial_access.1319384440
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2468548776
/workspace/coverage/default/46.sram_ctrl_ram_cfg.2377998122
/workspace/coverage/default/46.sram_ctrl_regwen.389365317
/workspace/coverage/default/46.sram_ctrl_smoke.2736512309
/workspace/coverage/default/46.sram_ctrl_stress_all.1114233694
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2447946677
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1908438736
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3093571528
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.2980013734
/workspace/coverage/default/47.sram_ctrl_alert_test.3503749428
/workspace/coverage/default/47.sram_ctrl_bijection.2295628369
/workspace/coverage/default/47.sram_ctrl_executable.2126601325
/workspace/coverage/default/47.sram_ctrl_lc_escalation.1809406568
/workspace/coverage/default/47.sram_ctrl_max_throughput.3800305616
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.2854075259
/workspace/coverage/default/47.sram_ctrl_mem_walk.2201494958
/workspace/coverage/default/47.sram_ctrl_multiple_keys.1920869269
/workspace/coverage/default/47.sram_ctrl_partial_access.3981469053
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2052449801
/workspace/coverage/default/47.sram_ctrl_ram_cfg.1860223436
/workspace/coverage/default/47.sram_ctrl_regwen.1160314064
/workspace/coverage/default/47.sram_ctrl_smoke.409632648
/workspace/coverage/default/47.sram_ctrl_stress_all.660104936
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.552980253
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3982989156
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.799952734
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.1146650621
/workspace/coverage/default/48.sram_ctrl_alert_test.3904209555
/workspace/coverage/default/48.sram_ctrl_bijection.2549604348
/workspace/coverage/default/48.sram_ctrl_executable.831734025
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2528146649
/workspace/coverage/default/48.sram_ctrl_max_throughput.172114266
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.1691114506
/workspace/coverage/default/48.sram_ctrl_mem_walk.857406595
/workspace/coverage/default/48.sram_ctrl_multiple_keys.129487491
/workspace/coverage/default/48.sram_ctrl_partial_access.3361561980
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.795682741
/workspace/coverage/default/48.sram_ctrl_ram_cfg.2947211084
/workspace/coverage/default/48.sram_ctrl_regwen.1443365049
/workspace/coverage/default/48.sram_ctrl_smoke.2786659740
/workspace/coverage/default/48.sram_ctrl_stress_all.2726352163
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3918080412
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2788040326
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1408323387
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2592261526
/workspace/coverage/default/49.sram_ctrl_alert_test.1904829885
/workspace/coverage/default/49.sram_ctrl_bijection.1610967254
/workspace/coverage/default/49.sram_ctrl_executable.739707022
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2236567272
/workspace/coverage/default/49.sram_ctrl_max_throughput.3671362343
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.812416233
/workspace/coverage/default/49.sram_ctrl_mem_walk.2447695876
/workspace/coverage/default/49.sram_ctrl_multiple_keys.418338980
/workspace/coverage/default/49.sram_ctrl_partial_access.3718608240
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1583052837
/workspace/coverage/default/49.sram_ctrl_ram_cfg.1531217184
/workspace/coverage/default/49.sram_ctrl_regwen.1851954323
/workspace/coverage/default/49.sram_ctrl_smoke.129592539
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1748572709
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.913016898
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1671569761
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3723154695
/workspace/coverage/default/5.sram_ctrl_alert_test.2004796932
/workspace/coverage/default/5.sram_ctrl_bijection.4188982883
/workspace/coverage/default/5.sram_ctrl_executable.4253892970
/workspace/coverage/default/5.sram_ctrl_lc_escalation.199379341
/workspace/coverage/default/5.sram_ctrl_max_throughput.854886835
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3090467663
/workspace/coverage/default/5.sram_ctrl_mem_walk.2260728773
/workspace/coverage/default/5.sram_ctrl_multiple_keys.691488805
/workspace/coverage/default/5.sram_ctrl_partial_access.128069988
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3307050291
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3436404884
/workspace/coverage/default/5.sram_ctrl_regwen.3468771378
/workspace/coverage/default/5.sram_ctrl_smoke.2427246829
/workspace/coverage/default/5.sram_ctrl_stress_all.3528971290
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.531918344
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.1906786526
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3352907102
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.3823543683
/workspace/coverage/default/6.sram_ctrl_alert_test.3173072218
/workspace/coverage/default/6.sram_ctrl_bijection.1759965972
/workspace/coverage/default/6.sram_ctrl_executable.4028625780
/workspace/coverage/default/6.sram_ctrl_lc_escalation.769464823
/workspace/coverage/default/6.sram_ctrl_max_throughput.1316559704
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1934547591
/workspace/coverage/default/6.sram_ctrl_mem_walk.39654826
/workspace/coverage/default/6.sram_ctrl_multiple_keys.2364141073
/workspace/coverage/default/6.sram_ctrl_partial_access.1907837489
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2567717520
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1493072881
/workspace/coverage/default/6.sram_ctrl_regwen.2630638598
/workspace/coverage/default/6.sram_ctrl_smoke.4004399007
/workspace/coverage/default/6.sram_ctrl_stress_all.1343293988
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2508097582
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2715470090
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2919144022
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1189872435
/workspace/coverage/default/7.sram_ctrl_alert_test.2765887824
/workspace/coverage/default/7.sram_ctrl_bijection.1746197217
/workspace/coverage/default/7.sram_ctrl_executable.1227018321
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2341009155
/workspace/coverage/default/7.sram_ctrl_max_throughput.3737869236
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3359926441
/workspace/coverage/default/7.sram_ctrl_mem_walk.1429440486
/workspace/coverage/default/7.sram_ctrl_multiple_keys.2222002681
/workspace/coverage/default/7.sram_ctrl_partial_access.3672276736
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2538438330
/workspace/coverage/default/7.sram_ctrl_ram_cfg.1672858504
/workspace/coverage/default/7.sram_ctrl_regwen.652099819
/workspace/coverage/default/7.sram_ctrl_smoke.1698935443
/workspace/coverage/default/7.sram_ctrl_stress_all.1089291689
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2532374642
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.482722321
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.3425135819
/workspace/coverage/default/8.sram_ctrl_alert_test.3980264941
/workspace/coverage/default/8.sram_ctrl_bijection.3536158341
/workspace/coverage/default/8.sram_ctrl_executable.1838730120
/workspace/coverage/default/8.sram_ctrl_lc_escalation.3454554774
/workspace/coverage/default/8.sram_ctrl_max_throughput.1254969956
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.2843731434
/workspace/coverage/default/8.sram_ctrl_mem_walk.1663419474
/workspace/coverage/default/8.sram_ctrl_multiple_keys.2251808897
/workspace/coverage/default/8.sram_ctrl_partial_access.2106960832
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2776160539
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3533111058
/workspace/coverage/default/8.sram_ctrl_regwen.613070896
/workspace/coverage/default/8.sram_ctrl_smoke.2119655443
/workspace/coverage/default/8.sram_ctrl_stress_all.1440359808
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1462303243
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.640381462
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3175128210
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3710599690
/workspace/coverage/default/9.sram_ctrl_alert_test.1071942962
/workspace/coverage/default/9.sram_ctrl_bijection.721057614
/workspace/coverage/default/9.sram_ctrl_executable.3921911086
/workspace/coverage/default/9.sram_ctrl_max_throughput.3334687968
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.4063268117
/workspace/coverage/default/9.sram_ctrl_mem_walk.640005069
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3347241200
/workspace/coverage/default/9.sram_ctrl_partial_access.3352292531
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.421006635
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1736135902
/workspace/coverage/default/9.sram_ctrl_regwen.999995600
/workspace/coverage/default/9.sram_ctrl_smoke.2868107718
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1179427476
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1951990293



Total test records in report: 1022
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/9.sram_ctrl_stress_pipeline.1179427476 Apr 30 01:42:00 PM PDT 24 Apr 30 01:44:33 PM PDT 24 3169123151 ps
T2 /workspace/coverage/default/15.sram_ctrl_stress_all.1225155861 Apr 30 01:42:21 PM PDT 24 Apr 30 03:10:58 PM PDT 24 76808044461 ps
T3 /workspace/coverage/default/41.sram_ctrl_smoke.155144370 Apr 30 01:44:55 PM PDT 24 Apr 30 01:45:01 PM PDT 24 568800924 ps
T7 /workspace/coverage/default/38.sram_ctrl_multiple_keys.1474190187 Apr 30 01:44:22 PM PDT 24 Apr 30 01:58:31 PM PDT 24 2652664893 ps
T8 /workspace/coverage/default/36.sram_ctrl_bijection.2501486015 Apr 30 01:44:07 PM PDT 24 Apr 30 01:44:53 PM PDT 24 3449633006 ps
T9 /workspace/coverage/default/2.sram_ctrl_bijection.3292526869 Apr 30 01:41:40 PM PDT 24 Apr 30 01:42:50 PM PDT 24 13200338367 ps
T4 /workspace/coverage/default/9.sram_ctrl_lc_escalation.1948335003 Apr 30 01:41:59 PM PDT 24 Apr 30 01:42:07 PM PDT 24 1728847335 ps
T10 /workspace/coverage/default/41.sram_ctrl_multiple_keys.567998754 Apr 30 01:44:55 PM PDT 24 Apr 30 01:47:20 PM PDT 24 630612492 ps
T11 /workspace/coverage/default/32.sram_ctrl_regwen.1097623211 Apr 30 01:43:53 PM PDT 24 Apr 30 01:52:05 PM PDT 24 1971493209 ps
T5 /workspace/coverage/default/46.sram_ctrl_lc_escalation.465077450 Apr 30 01:45:37 PM PDT 24 Apr 30 01:45:39 PM PDT 24 127801684 ps
T13 /workspace/coverage/default/28.sram_ctrl_bijection.2942064935 Apr 30 01:43:14 PM PDT 24 Apr 30 01:44:05 PM PDT 24 10518050656 ps
T31 /workspace/coverage/default/23.sram_ctrl_ram_cfg.459173630 Apr 30 01:42:57 PM PDT 24 Apr 30 01:42:59 PM PDT 24 35439942 ps
T12 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.219700802 Apr 30 01:45:33 PM PDT 24 Apr 30 01:53:07 PM PDT 24 20468964461 ps
T14 /workspace/coverage/default/40.sram_ctrl_partial_access.3664507991 Apr 30 01:44:43 PM PDT 24 Apr 30 01:47:05 PM PDT 24 2682293804 ps
T60 /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1741041972 Apr 30 01:42:01 PM PDT 24 Apr 30 01:45:36 PM PDT 24 11480168725 ps
T15 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3763000505 Apr 30 01:42:20 PM PDT 24 Apr 30 01:42:27 PM PDT 24 254816156 ps
T55 /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2761823901 Apr 30 01:42:37 PM PDT 24 Apr 30 01:47:19 PM PDT 24 12608679147 ps
T19 /workspace/coverage/default/42.sram_ctrl_alert_test.3353316585 Apr 30 01:45:09 PM PDT 24 Apr 30 01:45:10 PM PDT 24 12435116 ps
T56 /workspace/coverage/default/29.sram_ctrl_bijection.275135746 Apr 30 01:43:21 PM PDT 24 Apr 30 01:44:30 PM PDT 24 4031265221 ps
T57 /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.354136757 Apr 30 01:41:34 PM PDT 24 Apr 30 01:41:56 PM PDT 24 450294157 ps
T6 /workspace/coverage/default/12.sram_ctrl_lc_escalation.1519034502 Apr 30 01:42:15 PM PDT 24 Apr 30 01:42:23 PM PDT 24 2534410149 ps
T58 /workspace/coverage/default/6.sram_ctrl_bijection.1759965972 Apr 30 01:41:53 PM PDT 24 Apr 30 01:42:50 PM PDT 24 1695602327 ps
T20 /workspace/coverage/default/17.sram_ctrl_alert_test.3132208923 Apr 30 01:42:22 PM PDT 24 Apr 30 01:42:23 PM PDT 24 35219707 ps
T59 /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.3640117721 Apr 30 01:43:53 PM PDT 24 Apr 30 01:50:17 PM PDT 24 74815223681 ps
T29 /workspace/coverage/default/34.sram_ctrl_executable.3334000090 Apr 30 01:43:59 PM PDT 24 Apr 30 02:01:51 PM PDT 24 30964970670 ps
T71 /workspace/coverage/default/19.sram_ctrl_stress_pipeline.4235416306 Apr 30 01:42:30 PM PDT 24 Apr 30 01:45:07 PM PDT 24 3701541491 ps
T22 /workspace/coverage/default/35.sram_ctrl_stress_all.1326847652 Apr 30 01:44:07 PM PDT 24 Apr 30 01:50:42 PM PDT 24 137160730613 ps
T72 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.85956421 Apr 30 01:43:12 PM PDT 24 Apr 30 01:43:17 PM PDT 24 156534771 ps
T25 /workspace/coverage/default/49.sram_ctrl_lc_escalation.2236567272 Apr 30 01:46:07 PM PDT 24 Apr 30 01:46:15 PM PDT 24 1274224091 ps
T30 /workspace/coverage/default/8.sram_ctrl_stress_all.1440359808 Apr 30 01:42:01 PM PDT 24 Apr 30 02:06:21 PM PDT 24 12644312191 ps
T45 /workspace/coverage/default/41.sram_ctrl_access_during_key_req.4146020052 Apr 30 01:44:57 PM PDT 24 Apr 30 02:00:14 PM PDT 24 6880561303 ps
T73 /workspace/coverage/default/4.sram_ctrl_partial_access.2764144953 Apr 30 01:41:51 PM PDT 24 Apr 30 01:42:08 PM PDT 24 3231278018 ps
T32 /workspace/coverage/default/33.sram_ctrl_ram_cfg.3150453306 Apr 30 01:43:53 PM PDT 24 Apr 30 01:43:54 PM PDT 24 29023028 ps
T23 /workspace/coverage/default/46.sram_ctrl_regwen.389365317 Apr 30 01:45:39 PM PDT 24 Apr 30 01:55:06 PM PDT 24 10819265264 ps
T74 /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1469298801 Apr 30 01:45:11 PM PDT 24 Apr 30 01:48:06 PM PDT 24 5154865846 ps
T24 /workspace/coverage/default/17.sram_ctrl_regwen.256755558 Apr 30 01:42:24 PM PDT 24 Apr 30 01:47:42 PM PDT 24 6070086638 ps
T75 /workspace/coverage/default/35.sram_ctrl_regwen.1385984748 Apr 30 01:44:07 PM PDT 24 Apr 30 01:52:07 PM PDT 24 7303410566 ps
T130 /workspace/coverage/default/49.sram_ctrl_multiple_keys.418338980 Apr 30 01:46:04 PM PDT 24 Apr 30 02:03:46 PM PDT 24 36924606205 ps
T27 /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2521640684 Apr 30 01:41:43 PM PDT 24 Apr 30 01:41:49 PM PDT 24 144448010 ps
T122 /workspace/coverage/default/47.sram_ctrl_executable.2126601325 Apr 30 01:45:54 PM PDT 24 Apr 30 02:09:40 PM PDT 24 34253553003 ps
T123 /workspace/coverage/default/49.sram_ctrl_regwen.1851954323 Apr 30 01:46:08 PM PDT 24 Apr 30 01:47:01 PM PDT 24 1589757233 ps
T33 /workspace/coverage/default/4.sram_ctrl_ram_cfg.488246157 Apr 30 01:41:53 PM PDT 24 Apr 30 01:41:54 PM PDT 24 30342709 ps
T133 /workspace/coverage/default/42.sram_ctrl_mem_walk.2984735474 Apr 30 01:45:06 PM PDT 24 Apr 30 01:45:16 PM PDT 24 2254711909 ps
T134 /workspace/coverage/default/2.sram_ctrl_ram_cfg.2689718877 Apr 30 01:41:41 PM PDT 24 Apr 30 01:41:43 PM PDT 24 45664303 ps
T132 /workspace/coverage/default/28.sram_ctrl_max_throughput.809705603 Apr 30 01:43:20 PM PDT 24 Apr 30 01:45:08 PM PDT 24 788000786 ps
T46 /workspace/coverage/default/42.sram_ctrl_access_during_key_req.3581344653 Apr 30 01:45:04 PM PDT 24 Apr 30 02:07:52 PM PDT 24 47349049417 ps
T124 /workspace/coverage/default/33.sram_ctrl_regwen.3521946933 Apr 30 01:43:54 PM PDT 24 Apr 30 01:57:11 PM PDT 24 9875366005 ps
T135 /workspace/coverage/default/12.sram_ctrl_partial_access.757483285 Apr 30 01:42:11 PM PDT 24 Apr 30 01:44:09 PM PDT 24 1784297046 ps
T26 /workspace/coverage/default/11.sram_ctrl_stress_all.2857547648 Apr 30 01:42:13 PM PDT 24 Apr 30 02:45:06 PM PDT 24 14082028672 ps
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T147 /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1671569761 Apr 30 01:46:05 PM PDT 24 Apr 30 01:46:08 PM PDT 24 46503159 ps
T48 /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3392028056 Apr 30 01:44:20 PM PDT 24 Apr 30 01:50:32 PM PDT 24 2723799770 ps
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T155 /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.722936864 Apr 30 01:42:31 PM PDT 24 Apr 30 01:45:35 PM PDT 24 2833414862 ps
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T163 /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1583052837 Apr 30 01:46:03 PM PDT 24 Apr 30 01:51:55 PM PDT 24 65888043760 ps
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T84 /workspace/coverage/default/31.sram_ctrl_mem_partial_access.728259748 Apr 30 01:43:40 PM PDT 24 Apr 30 01:43:46 PM PDT 24 687869720 ps
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T85 /workspace/coverage/default/8.sram_ctrl_access_during_key_req.3425135819 Apr 30 01:42:00 PM PDT 24 Apr 30 01:43:31 PM PDT 24 1618371327 ps
T166 /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3175128210 Apr 30 01:41:59 PM PDT 24 Apr 30 01:42:06 PM PDT 24 62562075 ps
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T169 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2226265273 Apr 30 01:44:32 PM PDT 24 Apr 30 01:52:45 PM PDT 24 76162507631 ps
T170 /workspace/coverage/default/6.sram_ctrl_access_during_key_req.3823543683 Apr 30 01:41:50 PM PDT 24 Apr 30 01:46:36 PM PDT 24 3230278946 ps
T171 /workspace/coverage/default/35.sram_ctrl_executable.3464449321 Apr 30 01:44:00 PM PDT 24 Apr 30 01:59:01 PM PDT 24 5212865073 ps
T172 /workspace/coverage/default/29.sram_ctrl_stress_all.2363714176 Apr 30 01:43:25 PM PDT 24 Apr 30 02:56:01 PM PDT 24 16706977135 ps
T173 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.3084143755 Apr 30 01:44:58 PM PDT 24 Apr 30 01:45:03 PM PDT 24 64846408 ps
T126 /workspace/coverage/default/15.sram_ctrl_bijection.1544418156 Apr 30 01:42:21 PM PDT 24 Apr 30 01:42:55 PM PDT 24 3787354905 ps
T174 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.1108686495 Apr 30 01:44:46 PM PDT 24 Apr 30 01:44:51 PM PDT 24 156157615 ps
T175 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.4246077149 Apr 30 01:45:45 PM PDT 24 Apr 30 01:45:50 PM PDT 24 691943399 ps
T176 /workspace/coverage/default/42.sram_ctrl_bijection.2740832285 Apr 30 01:45:05 PM PDT 24 Apr 30 01:46:25 PM PDT 24 21522401746 ps
T177 /workspace/coverage/default/41.sram_ctrl_ram_cfg.777316763 Apr 30 01:44:59 PM PDT 24 Apr 30 01:45:00 PM PDT 24 30547019 ps
T178 /workspace/coverage/default/10.sram_ctrl_mem_partial_access.1584286846 Apr 30 01:42:11 PM PDT 24 Apr 30 01:42:17 PM PDT 24 683908049 ps
T179 /workspace/coverage/default/10.sram_ctrl_bijection.1476012404 Apr 30 01:42:03 PM PDT 24 Apr 30 01:42:51 PM PDT 24 2424107455 ps
T180 /workspace/coverage/default/44.sram_ctrl_executable.3579352318 Apr 30 01:45:19 PM PDT 24 Apr 30 01:53:21 PM PDT 24 53563175047 ps
T181 /workspace/coverage/default/40.sram_ctrl_max_throughput.3749158928 Apr 30 01:44:48 PM PDT 24 Apr 30 01:44:59 PM PDT 24 246736715 ps
T182 /workspace/coverage/default/27.sram_ctrl_bijection.1636924898 Apr 30 01:43:20 PM PDT 24 Apr 30 01:43:39 PM PDT 24 3959137064 ps
T183 /workspace/coverage/default/47.sram_ctrl_regwen.1160314064 Apr 30 01:45:53 PM PDT 24 Apr 30 01:58:25 PM PDT 24 42586811329 ps
T184 /workspace/coverage/default/2.sram_ctrl_stress_all.4078866394 Apr 30 01:41:47 PM PDT 24 Apr 30 02:22:38 PM PDT 24 201894855150 ps
T185 /workspace/coverage/default/21.sram_ctrl_ram_cfg.1093298503 Apr 30 01:42:45 PM PDT 24 Apr 30 01:42:47 PM PDT 24 351202601 ps
T186 /workspace/coverage/default/36.sram_ctrl_alert_test.4100617193 Apr 30 01:44:13 PM PDT 24 Apr 30 01:44:14 PM PDT 24 14303243 ps
T49 /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3871900119 Apr 30 01:43:48 PM PDT 24 Apr 30 01:44:37 PM PDT 24 278398072 ps
T187 /workspace/coverage/default/25.sram_ctrl_mem_partial_access.3849982989 Apr 30 01:43:05 PM PDT 24 Apr 30 01:43:09 PM PDT 24 133956365 ps
T188 /workspace/coverage/default/19.sram_ctrl_max_throughput.986927891 Apr 30 01:42:25 PM PDT 24 Apr 30 01:42:51 PM PDT 24 353660384 ps
T189 /workspace/coverage/default/43.sram_ctrl_alert_test.3662373856 Apr 30 01:45:12 PM PDT 24 Apr 30 01:45:13 PM PDT 24 14365050 ps
T190 /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.4190282037 Apr 30 01:43:06 PM PDT 24 Apr 30 01:43:36 PM PDT 24 96106390 ps
T191 /workspace/coverage/default/25.sram_ctrl_bijection.4069758501 Apr 30 01:43:03 PM PDT 24 Apr 30 01:44:10 PM PDT 24 14420911001 ps
T192 /workspace/coverage/default/43.sram_ctrl_stress_all.1364201845 Apr 30 01:45:11 PM PDT 24 Apr 30 02:06:46 PM PDT 24 24832497536 ps
T193 /workspace/coverage/default/25.sram_ctrl_stress_all.63319524 Apr 30 01:43:04 PM PDT 24 Apr 30 02:19:27 PM PDT 24 33472970621 ps
T194 /workspace/coverage/default/12.sram_ctrl_ram_cfg.1837382033 Apr 30 01:42:15 PM PDT 24 Apr 30 01:42:16 PM PDT 24 30952155 ps
T195 /workspace/coverage/default/15.sram_ctrl_access_during_key_req.3358236099 Apr 30 01:42:16 PM PDT 24 Apr 30 01:55:16 PM PDT 24 10204465907 ps
T196 /workspace/coverage/default/25.sram_ctrl_regwen.2886828461 Apr 30 01:43:05 PM PDT 24 Apr 30 01:50:17 PM PDT 24 7935735157 ps
T197 /workspace/coverage/default/45.sram_ctrl_mem_walk.2843318679 Apr 30 01:45:30 PM PDT 24 Apr 30 01:45:39 PM PDT 24 541405861 ps
T198 /workspace/coverage/default/13.sram_ctrl_multiple_keys.2573375953 Apr 30 01:42:12 PM PDT 24 Apr 30 02:08:01 PM PDT 24 95998516916 ps
T199 /workspace/coverage/default/6.sram_ctrl_multiple_keys.2364141073 Apr 30 01:41:47 PM PDT 24 Apr 30 01:52:47 PM PDT 24 29922177171 ps
T200 /workspace/coverage/default/10.sram_ctrl_stress_pipeline.290842606 Apr 30 01:42:08 PM PDT 24 Apr 30 01:45:22 PM PDT 24 2208393212 ps
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T202 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3248116681 Apr 30 01:42:23 PM PDT 24 Apr 30 01:45:49 PM PDT 24 11202303597 ps
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T204 /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.1342697417 Apr 30 01:44:27 PM PDT 24 Apr 30 01:50:20 PM PDT 24 18910623245 ps
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T207 /workspace/coverage/default/25.sram_ctrl_smoke.4153924411 Apr 30 01:43:07 PM PDT 24 Apr 30 01:44:53 PM PDT 24 135938854 ps
T208 /workspace/coverage/default/22.sram_ctrl_regwen.2740044268 Apr 30 01:42:51 PM PDT 24 Apr 30 02:00:04 PM PDT 24 13089433661 ps
T209 /workspace/coverage/default/47.sram_ctrl_stress_pipeline.3982989156 Apr 30 01:45:44 PM PDT 24 Apr 30 01:50:50 PM PDT 24 3309909469 ps
T210 /workspace/coverage/default/35.sram_ctrl_max_throughput.2324497813 Apr 30 01:44:00 PM PDT 24 Apr 30 01:44:29 PM PDT 24 1502038336 ps
T211 /workspace/coverage/default/4.sram_ctrl_alert_test.3864247615 Apr 30 01:41:50 PM PDT 24 Apr 30 01:41:51 PM PDT 24 41229243 ps
T212 /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.482722321 Apr 30 01:42:01 PM PDT 24 Apr 30 01:43:00 PM PDT 24 455885605 ps
T213 /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.403497292 Apr 30 01:44:34 PM PDT 24 Apr 30 01:45:09 PM PDT 24 124612783 ps
T214 /workspace/coverage/default/25.sram_ctrl_lc_escalation.4010717736 Apr 30 01:43:04 PM PDT 24 Apr 30 01:43:12 PM PDT 24 2076906375 ps
T215 /workspace/coverage/default/7.sram_ctrl_mem_partial_access.3359926441 Apr 30 01:41:58 PM PDT 24 Apr 30 01:42:01 PM PDT 24 84399044 ps
T216 /workspace/coverage/default/17.sram_ctrl_bijection.3910210199 Apr 30 01:42:25 PM PDT 24 Apr 30 01:43:24 PM PDT 24 9695304672 ps
T217 /workspace/coverage/default/2.sram_ctrl_executable.346897029 Apr 30 01:41:42 PM PDT 24 Apr 30 01:54:10 PM PDT 24 28857301289 ps
T218 /workspace/coverage/default/29.sram_ctrl_partial_access.549914568 Apr 30 01:43:20 PM PDT 24 Apr 30 01:43:28 PM PDT 24 153768226 ps
T219 /workspace/coverage/default/18.sram_ctrl_access_during_key_req.94141557 Apr 30 01:42:20 PM PDT 24 Apr 30 01:44:33 PM PDT 24 778289283 ps
T220 /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1102157179 Apr 30 01:42:10 PM PDT 24 Apr 30 01:47:13 PM PDT 24 13753098678 ps
T221 /workspace/coverage/default/26.sram_ctrl_mem_walk.1273486102 Apr 30 01:43:03 PM PDT 24 Apr 30 01:43:13 PM PDT 24 568913565 ps
T222 /workspace/coverage/default/16.sram_ctrl_partial_access.664462968 Apr 30 01:42:24 PM PDT 24 Apr 30 01:42:45 PM PDT 24 1173295965 ps
T223 /workspace/coverage/default/40.sram_ctrl_ram_cfg.727756871 Apr 30 01:44:55 PM PDT 24 Apr 30 01:44:56 PM PDT 24 50319149 ps
T224 /workspace/coverage/default/27.sram_ctrl_access_during_key_req.4286488962 Apr 30 01:43:14 PM PDT 24 Apr 30 01:54:13 PM PDT 24 3281816535 ps
T225 /workspace/coverage/default/31.sram_ctrl_multiple_keys.2572446175 Apr 30 01:43:35 PM PDT 24 Apr 30 01:53:59 PM PDT 24 3513775717 ps
T226 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1408323387 Apr 30 01:45:57 PM PDT 24 Apr 30 01:48:03 PM PDT 24 159247841 ps
T227 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.1676288449 Apr 30 01:44:32 PM PDT 24 Apr 30 01:44:36 PM PDT 24 168672142 ps
T228 /workspace/coverage/default/9.sram_ctrl_ram_cfg.1736135902 Apr 30 01:42:08 PM PDT 24 Apr 30 01:42:10 PM PDT 24 32243206 ps
T229 /workspace/coverage/default/43.sram_ctrl_smoke.2616628275 Apr 30 01:45:06 PM PDT 24 Apr 30 01:46:04 PM PDT 24 573565335 ps
T230 /workspace/coverage/default/48.sram_ctrl_ram_cfg.2947211084 Apr 30 01:45:56 PM PDT 24 Apr 30 01:45:57 PM PDT 24 96346464 ps
T231 /workspace/coverage/default/1.sram_ctrl_alert_test.2640333405 Apr 30 01:41:39 PM PDT 24 Apr 30 01:41:40 PM PDT 24 74473844 ps
T232 /workspace/coverage/default/17.sram_ctrl_smoke.4032744895 Apr 30 01:42:24 PM PDT 24 Apr 30 01:42:46 PM PDT 24 1445370127 ps
T233 /workspace/coverage/default/39.sram_ctrl_executable.45059117 Apr 30 01:44:42 PM PDT 24 Apr 30 01:58:10 PM PDT 24 10727913559 ps
T234 /workspace/coverage/default/46.sram_ctrl_ram_cfg.2377998122 Apr 30 01:45:45 PM PDT 24 Apr 30 01:45:47 PM PDT 24 32087543 ps
T235 /workspace/coverage/default/41.sram_ctrl_max_throughput.2617777290 Apr 30 01:44:50 PM PDT 24 Apr 30 01:45:23 PM PDT 24 86523003 ps
T236 /workspace/coverage/default/33.sram_ctrl_smoke.2261368012 Apr 30 01:43:46 PM PDT 24 Apr 30 01:43:49 PM PDT 24 301536962 ps
T50 /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2420250719 Apr 30 01:42:49 PM PDT 24 Apr 30 01:46:12 PM PDT 24 5270499731 ps
T237 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.2854075259 Apr 30 01:45:53 PM PDT 24 Apr 30 01:45:56 PM PDT 24 49610134 ps
T238 /workspace/coverage/default/21.sram_ctrl_stress_all.22352388 Apr 30 01:42:41 PM PDT 24 Apr 30 02:02:20 PM PDT 24 85772263512 ps
T239 /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2052449801 Apr 30 01:45:43 PM PDT 24 Apr 30 01:50:55 PM PDT 24 24901940246 ps
T240 /workspace/coverage/default/1.sram_ctrl_access_during_key_req.2483878403 Apr 30 01:41:39 PM PDT 24 Apr 30 01:47:15 PM PDT 24 2754402474 ps
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T242 /workspace/coverage/default/49.sram_ctrl_partial_access.3718608240 Apr 30 01:46:04 PM PDT 24 Apr 30 01:46:20 PM PDT 24 1482747334 ps
T243 /workspace/coverage/default/2.sram_ctrl_mem_partial_access.2599816718 Apr 30 01:41:41 PM PDT 24 Apr 30 01:41:46 PM PDT 24 120428663 ps
T244 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.1987138162 Apr 30 01:42:58 PM PDT 24 Apr 30 01:43:04 PM PDT 24 152000752 ps
T245 /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.4197741080 Apr 30 01:45:07 PM PDT 24 Apr 30 01:46:36 PM PDT 24 465487062 ps
T246 /workspace/coverage/default/17.sram_ctrl_lc_escalation.153941363 Apr 30 01:42:29 PM PDT 24 Apr 30 01:42:33 PM PDT 24 455043647 ps
T247 /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.413641012 Apr 30 01:42:25 PM PDT 24 Apr 30 01:48:10 PM PDT 24 129151278511 ps
T248 /workspace/coverage/default/48.sram_ctrl_max_throughput.172114266 Apr 30 01:45:54 PM PDT 24 Apr 30 01:47:12 PM PDT 24 426503537 ps
T249 /workspace/coverage/default/25.sram_ctrl_ram_cfg.276694947 Apr 30 01:43:04 PM PDT 24 Apr 30 01:43:05 PM PDT 24 44298902 ps
T250 /workspace/coverage/default/34.sram_ctrl_mem_partial_access.1105194702 Apr 30 01:43:59 PM PDT 24 Apr 30 01:44:05 PM PDT 24 123258655 ps
T251 /workspace/coverage/default/30.sram_ctrl_mem_walk.3417300612 Apr 30 01:43:35 PM PDT 24 Apr 30 01:43:45 PM PDT 24 447795059 ps
T252 /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3189934882 Apr 30 01:44:50 PM PDT 24 Apr 30 01:49:04 PM PDT 24 22349108369 ps
T253 /workspace/coverage/default/0.sram_ctrl_stress_all.3753648085 Apr 30 01:41:39 PM PDT 24 Apr 30 02:19:37 PM PDT 24 11731302333 ps
T254 /workspace/coverage/default/19.sram_ctrl_mem_walk.4072318150 Apr 30 01:42:30 PM PDT 24 Apr 30 01:42:38 PM PDT 24 1839209362 ps
T255 /workspace/coverage/default/26.sram_ctrl_bijection.1001950352 Apr 30 01:43:06 PM PDT 24 Apr 30 01:43:34 PM PDT 24 5273181856 ps
T256 /workspace/coverage/default/40.sram_ctrl_stress_pipeline.1479992747 Apr 30 01:44:49 PM PDT 24 Apr 30 01:47:45 PM PDT 24 1921327668 ps
T257 /workspace/coverage/default/39.sram_ctrl_stress_all.1161485350 Apr 30 01:44:48 PM PDT 24 Apr 30 02:21:13 PM PDT 24 151806628526 ps
T258 /workspace/coverage/default/45.sram_ctrl_regwen.1513631828 Apr 30 01:45:34 PM PDT 24 Apr 30 02:08:52 PM PDT 24 71890784561 ps
T259 /workspace/coverage/default/4.sram_ctrl_multiple_keys.35864042 Apr 30 01:41:50 PM PDT 24 Apr 30 01:46:34 PM PDT 24 4575569322 ps
T260 /workspace/coverage/default/13.sram_ctrl_lc_escalation.1837439137 Apr 30 01:42:18 PM PDT 24 Apr 30 01:42:24 PM PDT 24 395955143 ps
T261 /workspace/coverage/default/45.sram_ctrl_bijection.3594872987 Apr 30 01:45:23 PM PDT 24 Apr 30 01:45:43 PM PDT 24 909187924 ps
T262 /workspace/coverage/default/14.sram_ctrl_multiple_keys.3854197160 Apr 30 01:42:13 PM PDT 24 Apr 30 01:45:20 PM PDT 24 5395641273 ps
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T264 /workspace/coverage/default/35.sram_ctrl_stress_pipeline.2753694439 Apr 30 01:44:04 PM PDT 24 Apr 30 01:49:02 PM PDT 24 12739603526 ps
T265 /workspace/coverage/default/19.sram_ctrl_access_during_key_req.3544198900 Apr 30 01:42:27 PM PDT 24 Apr 30 01:44:37 PM PDT 24 2227458838 ps
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T269 /workspace/coverage/default/34.sram_ctrl_max_throughput.3418512156 Apr 30 01:43:54 PM PDT 24 Apr 30 01:44:04 PM PDT 24 70553502 ps
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T280 /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3898909628 Apr 30 01:42:21 PM PDT 24 Apr 30 01:49:14 PM PDT 24 23737197508 ps
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T300 /workspace/coverage/default/9.sram_ctrl_executable.3921911086 Apr 30 01:42:00 PM PDT 24 Apr 30 01:59:34 PM PDT 24 48845150879 ps
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T302 /workspace/coverage/default/26.sram_ctrl_smoke.374218917 Apr 30 01:43:04 PM PDT 24 Apr 30 01:43:09 PM PDT 24 2567584790 ps
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T306 /workspace/coverage/default/5.sram_ctrl_access_during_key_req.3723154695 Apr 30 01:41:50 PM PDT 24 Apr 30 01:56:41 PM PDT 24 3376157342 ps
T307 /workspace/coverage/default/21.sram_ctrl_access_during_key_req.3060095479 Apr 30 01:42:43 PM PDT 24 Apr 30 01:59:14 PM PDT 24 55886454401 ps
T308 /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2956101792 Apr 30 01:42:26 PM PDT 24 Apr 30 01:43:30 PM PDT 24 231656305 ps
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T310 /workspace/coverage/default/43.sram_ctrl_partial_access.1638769664 Apr 30 01:45:11 PM PDT 24 Apr 30 01:45:28 PM PDT 24 1315094690 ps
T311 /workspace/coverage/default/28.sram_ctrl_lc_escalation.530825270 Apr 30 01:43:18 PM PDT 24 Apr 30 01:43:23 PM PDT 24 368043224 ps
T312 /workspace/coverage/default/2.sram_ctrl_multiple_keys.2289711982 Apr 30 01:41:38 PM PDT 24 Apr 30 01:44:20 PM PDT 24 11222910186 ps
T313 /workspace/coverage/default/5.sram_ctrl_partial_access.128069988 Apr 30 01:41:49 PM PDT 24 Apr 30 01:42:05 PM PDT 24 612739205 ps
T314 /workspace/coverage/default/18.sram_ctrl_executable.2999254257 Apr 30 01:42:22 PM PDT 24 Apr 30 01:57:05 PM PDT 24 13815094329 ps
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