Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	42364327	1			T1	116061		T2	340993		T3	2787
triple_byte_access	2447950	1			T1	2297		T2	5619		T3	60
halfword_access	3678136	1			T1	3500		T2	8317		T3	84
byte_access	4911384	1			T1	4692		T2	11117		T3	122
zero_access	1238580	1			T1	1177		T2	2819		T3	29

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27263778

1

T1

63918

T2

184363

T3

1499

auto[1]

27376599

1

T1

63809

T2

184502

T3

1583

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21130883	1			T1	58025		T2	170433		T3	1338
auto[0]	triple_byte_access	1220366	1			T1	1166		T2	2818		T3	39
auto[0]	halfword_access	1835681	1			T1	1738		T2	4183		T3	38
auto[0]	byte_access	2453291	1			T1	2388		T2	5545		T3	71
auto[0]	zero_access	623557	1			T1	601		T2	1384		T3	13
auto[1]	word_access	21233444	1			T1	58036		T2	170560		T3	1449
auto[1]	triple_byte_access	1227584	1			T1	1131		T2	2801		T3	21
auto[1]	halfword_access	1842455	1			T1	1762		T2	4134		T3	46
auto[1]	byte_access	2458093	1			T1	2304		T2	5572		T3	51
auto[1]	zero_access	615023	1			T1	576		T2	1435		T3	16