Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13467699

1

T1

1843

T2

10728

T3

9

full_word

53116058

1

T1

106

T2

107386

T3

103

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	66583447	1			T1	1949		T2	118114		T3	112
auto[TlIntgErrCmd]	95	1			T101	7		T102	3		T103	4
auto[TlIntgErrData]	96	1			T101	5		T102	3		T103	4
auto[TlIntgErrBoth]	119	1			T101	8		T102	4		T103	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30263780

1

T1

851

T2

44333

T3

49

auto[1]

36319977

1

T1

1098

T2

73781

T3

63

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6409718	1			T1	843		T2	3960		T3	6
auto[TlIntgErrNone]	partial	auto[1]	7057700	1			T1	1000		T2	6768		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	23853937	1			T1	8		T2	40373		T3	43
auto[TlIntgErrNone]	full_word	auto[1]	29262092	1			T1	98		T2	67013		T3	60
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T101	3		T103	2		T119	3
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T101	3		T102	3		T103	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T101	1		T127	1		T126	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T119	1		T122	1		T120	1
auto[TlIntgErrData]	partial	auto[0]	39	1			T101	1		T102	1		T103	2
auto[TlIntgErrData]	partial	auto[1]	46	1			T101	4		T102	2		T103	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T124	1		T123	1		T128	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T129	1		T125	3		T130	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T101	5		T102	2		T103	1
auto[TlIntgErrBoth]	partial	auto[1]	69	1			T101	3		T102	2		T103	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T119	1		T128	2		T129	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T123	1		T128	2		T126	1