Group : dv_base_reg_pkg::mubi_cov#(8,32'h00000096,32'h00000069)::mubi_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : dv_base_reg_pkg::mubi_cov#(8,32'h00000096,32'h00000069)::mubi_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
mubi8_cov_of_mubi8_cov_of_tb.dut.u_otp_en_sram_ifetch_mubi_cov_if 100.00 1 100 1 64 64




Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.u_otp_en_sram_ifetch_mubi_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.u_otp_en_sram_ifetch_mubi_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00


Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.u_otp_en_sram_ifetch_mubi_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 10 0 10 100.00 100 1 1 0


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 64 1 T11 1 T22 1 T54 1
others[1] 58 1 T2 1 T11 2 T54 1
others[2] 74 1 T11 3 T72 1 T134 1
others[3] 58 1 T23 2 T57 1 T49 1
others[4] 71 1 T11 2 T23 2 T58 1
others[5] 69 1 T2 2 T11 2 T72 2
others[6] 73 1 T11 3 T22 1 T6 2
others[7] 68 1 T11 1 T54 1 T6 1
false 5394 1 T1 1 T2 5 T3 14
true 726 1 T2 6 T11 20 T54 6

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%