Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	655117	1			T3	5		T12	683		T13	20863
auto[1]	9699295	1			T1	768		T2	3264		T3	4
auto[2]	544506	1			T3	8		T12	612		T13	17847
auto[3]	9600332	1			T1	991		T2	3297		T3	4

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13639980	1			T1	8		T2	5448		T3	16
auto[1]	1928544	1			T1	98		T2	545		T3	4
auto[2]	1919291	1			T1	162		T2	521		T3	1
auto[3]	3011435	1			T1	1491		T2	47		T4	255

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8526532

1

T1

1759

T2

6551

T3

21

auto[1]

11972718

1

T2

10

T5

9

T10

178055

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	233334	1			T3	5		T12	546		T137	376
auto[0]	auto[0]	auto[1]	24145	1			T12	56		T137	47		T44	27
auto[0]	auto[0]	auto[2]	24369	1			T12	73		T137	48		T44	31
auto[0]	auto[0]	auto[3]	8403	1			T12	5		T13	3		T137	1
auto[0]	auto[1]	auto[0]	3268874	1			T2	2714		T3	3		T5	4837
auto[0]	auto[1]	auto[1]	341926	1			T1	8		T2	252		T3	1
auto[0]	auto[1]	auto[2]	329685	1			T1	84		T2	276		T4	3
auto[0]	auto[1]	auto[3]	72392	1			T1	676		T2	18		T4	109
auto[0]	auto[2]	auto[0]	199308	1			T3	5		T12	493		T13	1
auto[0]	auto[2]	auto[1]	20624	1			T3	3		T12	57		T137	34
auto[0]	auto[2]	auto[2]	19171	1			T12	56		T137	28		T44	26
auto[0]	auto[2]	auto[3]	6219	1			T12	6		T13	2		T137	1
auto[0]	auto[3]	auto[0]	3237095	1			T1	8		T2	2725		T3	3
auto[0]	auto[3]	auto[1]	326658	1			T1	90		T2	292		T4	4
auto[0]	auto[3]	auto[2]	339598	1			T1	78		T2	245		T3	1
auto[0]	auto[3]	auto[3]	74731	1			T1	815		T2	29		T4	146
auto[1]	auto[0]	auto[0]	12290	1			T12	3		T13	705		T135	703
auto[1]	auto[0]	auto[1]	54398	1			T13	3074		T135	3231		T46	1
auto[1]	auto[0]	auto[2]	54111	1			T13	3098		T135	3126		T138	1689
auto[1]	auto[0]	auto[3]	244067	1			T13	13983		T135	14294		T136	1
auto[1]	auto[1]	auto[0]	3341917	1			T2	4		T5	5		T10	73809
auto[1]	auto[1]	auto[1]	581014	1			T10	7410		T11	3		T96	1956
auto[1]	auto[1]	auto[2]	537671	1			T10	7381		T54	1		T96	626
auto[1]	auto[1]	auto[3]	1225816	1			T10	748		T96	8623		T70	881
auto[1]	auto[2]	auto[0]	10762	1			T13	677		T44	1		T135	648
auto[1]	auto[2]	auto[1]	47486	1			T13	2719		T44	1		T135	2887
auto[1]	auto[2]	auto[2]	43630	1			T13	2600		T135	2139		T139	1
auto[1]	auto[2]	auto[3]	197306	1			T13	11848		T135	9807		T140	1
auto[1]	auto[3]	auto[0]	3336400	1			T2	5		T5	4		T10	73014
auto[1]	auto[3]	auto[1]	532293	1			T2	1		T10	7456		T54	1
auto[1]	auto[3]	auto[2]	571056	1			T10	7503		T52	1		T54	1
auto[1]	auto[3]	auto[3]	1182501	1			T10	734		T52	1		T96	8609