Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	342017695	135723	0	0
ctrl_regwen_rd_A	342017695	7439	0	0
exec_rd_A	342017695	7004	0	0
exec_regwen_rd_A	342017695	7802	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342017695	135723	0	0
T15	228129	3916	0	0
T16	11664	0	0	0
T20	1063	0	0	0
T22	125708	0	0	0
T23	0	2439	0	0
T25	3042	0	0	0
T26	70546	2236	0	0
T27	0	3553	0	0
T44	0	2077	0	0
T47	0	4844	0	0
T48	0	762	0	0
T49	0	2655	0	0
T50	0	2657	0	0
T51	0	969	0	0
T52	8205	0	0	0
T53	359270	0	0	0
T54	289495	0	0	0
T55	7829	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342017695	7439	0	0
T35	0	504	0	0
T48	45572	162	0	0
T56	62203	0	0	0
T79	3955	0	0	0
T99	148249	0	0	0
T100	140176	0	0	0
T104	0	267	0	0
T105	0	147	0	0
T106	0	181	0	0
T107	0	811	0	0
T108	0	507	0	0
T109	0	1050	0	0
T110	0	90	0	0
T111	0	461	0	0
T112	14686	0	0	0
T113	3037	0	0	0
T114	264635	0	0	0
T115	33448	0	0	0
T116	394488	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342017695	7004	0	0
T35	0	317	0	0
T48	45572	149	0	0
T56	62203	0	0	0
T79	3955	0	0	0
T99	148249	0	0	0
T100	140176	0	0	0
T104	0	217	0	0
T105	0	129	0	0
T106	0	135	0	0
T107	0	860	0	0
T108	0	433	0	0
T109	0	977	0	0
T110	0	83	0	0
T111	0	485	0	0
T112	14686	0	0	0
T113	3037	0	0	0
T114	264635	0	0	0
T115	33448	0	0	0
T116	394488	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342017695	7802	0	0
T35	0	550	0	0
T48	45572	184	0	0
T56	62203	0	0	0
T79	3955	0	0	0
T99	148249	0	0	0
T100	140176	0	0	0
T104	0	247	0	0
T105	0	183	0	0
T106	0	169	0	0
T107	0	855	0	0
T108	0	382	0	0
T109	0	913	0	0
T110	0	73	0	0
T111	0	601	0	0
T112	14686	0	0	0
T113	3037	0	0	0
T114	264635	0	0	0
T115	33448	0	0	0
T116	394488	0	0	0