Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	150672788	1			T1	6142		T2	4422		T3	281012
instr_valid_dis	122130407	1			T1	6142		T2	4422		T3	281012
instr_en	19833987	1			T13	318736		T19	301220		T16	9380

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10597556	1			T13	62308		T19	45588		T16	9380
sram_ifetch_valid_disable	117756764	1			T1	6142		T2	4422		T3	281012
sram_ifetch_enable	22318468	1			T13	114048		T18	9860		T19	185110

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	150672788	1			T1	6142		T2	4422		T3	281012
hw_debug_en_valid_off	117545351	1			T1	6142		T2	4422		T3	281012
hw_debug_en_on	22772679	1			T13	198080		T19	68920		T7	486820

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	117756764	1			T1	6142		T2	4422		T3	281012
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	106543233	1			T1	6142		T2	4422		T3	281012
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8127777	1			T13	142454		T19	98336		T7	57472
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3918579	1			T19	11046		T16	9380		T7	41486
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1997169	1			T7	20950		T36	50806		T54	19414
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1261966	1			T19	11046		T16	9380		T7	20536
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4831427	1			T13	62308		T19	34542		T7	110114
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2242759	1			T7	92314		T27	24754		T54	25576
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1702978	1			T13	62308		T19	34542		T7	17800
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8646082	1			T13	53012		T19	34378		T7	213794
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4415854	1			T7	158746		T36	64470		T44	1942
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3014938	1			T13	53012		T19	34378		T7	31376

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8033176	1			T13	113974		T19	157296		T7	43406
lc_exec_en	9295170	1			T13	82760		T7	162912		T36	82
valid_exec_dis	115432284	1			T1	6142		T2	4422		T3	281012
invalid_exec_dis	32916024	1			T13	176356		T18	9860		T19	230698