Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.08	99.81	96.99	100.00	100.00	98.57	99.70	98.52

Total tests in report: 1033

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
79.20	79.20	96.30	96.30	73.25	73.25	89.70	89.70	71.43	71.43	87.90	87.90	94.45	94.45	41.37	41.37	/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.4228792042
89.06	9.86	98.64	2.34	85.19	11.95	97.21	7.51	100.00	28.57	94.24	6.34	94.90	0.45	53.25	11.87	/workspace/coverage/default/28.sram_ctrl_stress_all.2717974528
95.44	6.38	99.12	0.49	89.87	4.68	98.18	0.97	100.00	0.00	95.97	1.73	96.25	1.35	88.68	35.44	/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.511618428
96.45	1.01	99.51	0.39	92.08	2.21	99.11	0.93	100.00	0.00	97.98	2.02	96.85	0.60	89.61	0.93	/workspace/coverage/default/2.sram_ctrl_sec_cm.728105249
97.22	0.77	99.51	0.00	92.47	0.39	99.11	0.00	100.00	0.00	97.98	0.00	96.85	0.00	94.62	5.01	/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3959503030
97.58	0.36	99.51	0.00	92.86	0.39	99.11	0.00	100.00	0.00	98.27	0.29	96.85	0.00	96.47	1.86	/workspace/coverage/default/37.sram_ctrl_regwen.4158759707
97.82	0.24	99.51	0.00	93.12	0.26	99.18	0.07	100.00	0.00	98.27	0.00	98.20	1.35	96.47	0.00	/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.181332457
98.05	0.23	99.81	0.29	93.12	0.00	99.93	0.75	100.00	0.00	98.85	0.58	98.20	0.00	96.47	0.00	/workspace/coverage/default/29.sram_ctrl_ram_cfg.1069016624
98.20	0.15	99.81	0.00	93.25	0.13	99.93	0.00	100.00	0.00	98.85	0.00	99.10	0.90	96.47	0.00	/workspace/coverage/default/18.sram_ctrl_access_during_key_req.1996249308
98.33	0.13	99.81	0.00	93.25	0.00	99.93	0.00	100.00	0.00	98.85	0.00	99.10	0.00	97.40	0.93	/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.419255689
98.42	0.09	99.81	0.00	93.64	0.39	100.00	0.07	100.00	0.00	98.85	0.00	99.25	0.15	97.40	0.00	/workspace/coverage/default/33.sram_ctrl_alert_test.2963485752
98.49	0.07	99.81	0.00	93.77	0.13	100.00	0.00	100.00	0.00	98.85	0.00	99.25	0.00	97.77	0.37	/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3755864722
98.56	0.06	99.81	0.00	93.77	0.00	100.00	0.00	100.00	0.00	98.85	0.00	99.70	0.45	97.77	0.00	/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.552495462
98.62	0.06	99.81	0.00	94.03	0.26	100.00	0.00	100.00	0.00	98.85	0.00	99.70	0.00	97.96	0.19	/workspace/coverage/default/24.sram_ctrl_lc_escalation.3327779492
98.67	0.05	99.81	0.00	94.03	0.00	100.00	0.00	100.00	0.00	98.85	0.00	99.70	0.00	98.33	0.37	/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2531814801
98.70	0.03	99.81	0.00	94.03	0.00	100.00	0.00	100.00	0.00	98.85	0.00	99.70	0.00	98.52	0.19	/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2511701667
98.72	0.02	99.81	0.00	94.16	0.13	100.00	0.00	100.00	0.00	98.85	0.00	99.70	0.00	98.52	0.00	/workspace/coverage/default/0.sram_ctrl_lc_escalation.2303061100

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1441292943
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2931775531
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.267821850
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3579063120
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4290786607
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.822376997
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1362468064
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2331358842
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3479355134
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.4280572264
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.609099732
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.44549890
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1523220125
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1244110925
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1563399945
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1932786324
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1939272340
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1511924397
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2010162310
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.88222372
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.17791912
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.997118454
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2791117506
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1012128751
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.541547803
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4284839727
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.330975087
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3192959433
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2951632253
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3426215756
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3183934912
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3162497978
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2756642744
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1816328284
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.76961755
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.674162811
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2686539616
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.83654057
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3366505044
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1877337625
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.630982924
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.393436983
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3859142154
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1326143276
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3196335232
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1557136434
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3761360994
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3413526885
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1314839446
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3551634134
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.31549695
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1006801809
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.925583978
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.29718682
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3124811597
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.40462132
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.646063079
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3948416401
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2222197653
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.279832883
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2095510533
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4067573784
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2163310169
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1670470706
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1019473018
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1458428822
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1454480052
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.815546574
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3852848502
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.489134818
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3420513371
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3111362692
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.775577305
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1225472519
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2969397659
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1894705144
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.688577029
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3744974006
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.441925030
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1009974831
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2931720771
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.122192064
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2657782128
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2190261901
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1530016083
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.398420032
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.811555909
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1100606977
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3253081668
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2353756615
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2400927476
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2219474254
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2164858723
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3552700613
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.308264654
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1441259551
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2558404031
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1761813838
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2535388971
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3424514540
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.36141379
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1241886491
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3786590688
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.406710972
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2694662336
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3315628863
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3172774743
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2519053164
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2973808513
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3398442374
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3903979077
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1234921505
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2367004390
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.4240360614
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2549743537
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.909588137
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.164815696
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1863655415
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3545872148
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.4269872834
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2727359660
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3854390227
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.707562576
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1174858572
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4215930642
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2190678102
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1174219789
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2034061443
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2506650918
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2805433322
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.922297845
/workspace/coverage/default/0.sram_ctrl_alert_test.2328276091
/workspace/coverage/default/0.sram_ctrl_bijection.1548035524
/workspace/coverage/default/0.sram_ctrl_executable.2853652200
/workspace/coverage/default/0.sram_ctrl_max_throughput.1844758341
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.2400157752
/workspace/coverage/default/0.sram_ctrl_mem_walk.2601064769
/workspace/coverage/default/0.sram_ctrl_multiple_keys.1934815878
/workspace/coverage/default/0.sram_ctrl_partial_access.425903308
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2433644401
/workspace/coverage/default/0.sram_ctrl_ram_cfg.1242118942
/workspace/coverage/default/0.sram_ctrl_regwen.309972255
/workspace/coverage/default/0.sram_ctrl_sec_cm.897150482
/workspace/coverage/default/0.sram_ctrl_smoke.2666307437
/workspace/coverage/default/0.sram_ctrl_stress_all.2546072760
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1530514225
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.1322920186
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2343253349
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.1505459655
/workspace/coverage/default/1.sram_ctrl_alert_test.3862578485
/workspace/coverage/default/1.sram_ctrl_bijection.2914529850
/workspace/coverage/default/1.sram_ctrl_executable.2975670477
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3011000415
/workspace/coverage/default/1.sram_ctrl_max_throughput.2106342550
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.2209857831
/workspace/coverage/default/1.sram_ctrl_mem_walk.2353343903
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2756244670
/workspace/coverage/default/1.sram_ctrl_partial_access.1554390535
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1374767649
/workspace/coverage/default/1.sram_ctrl_ram_cfg.4035423075
/workspace/coverage/default/1.sram_ctrl_regwen.1383477907
/workspace/coverage/default/1.sram_ctrl_sec_cm.4284292012
/workspace/coverage/default/1.sram_ctrl_smoke.884864832
/workspace/coverage/default/1.sram_ctrl_stress_all.2885731950
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1701542638
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.506907013
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3854978090
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.1374611702
/workspace/coverage/default/10.sram_ctrl_alert_test.3643771212
/workspace/coverage/default/10.sram_ctrl_bijection.3003838541
/workspace/coverage/default/10.sram_ctrl_executable.4004434402
/workspace/coverage/default/10.sram_ctrl_lc_escalation.4118478606
/workspace/coverage/default/10.sram_ctrl_max_throughput.1352078473
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.1947443713
/workspace/coverage/default/10.sram_ctrl_mem_walk.3099456794
/workspace/coverage/default/10.sram_ctrl_multiple_keys.3746365198
/workspace/coverage/default/10.sram_ctrl_partial_access.909245795
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1392886418
/workspace/coverage/default/10.sram_ctrl_ram_cfg.2788284127
/workspace/coverage/default/10.sram_ctrl_regwen.3972639866
/workspace/coverage/default/10.sram_ctrl_smoke.2802854282
/workspace/coverage/default/10.sram_ctrl_stress_all.1935406150
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.465209229
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1167911061
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.894989332
/workspace/coverage/default/11.sram_ctrl_alert_test.2153235806
/workspace/coverage/default/11.sram_ctrl_bijection.934974003
/workspace/coverage/default/11.sram_ctrl_executable.1596203297
/workspace/coverage/default/11.sram_ctrl_lc_escalation.4148898941
/workspace/coverage/default/11.sram_ctrl_max_throughput.1465498381
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.67640217
/workspace/coverage/default/11.sram_ctrl_mem_walk.151456042
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3227053666
/workspace/coverage/default/11.sram_ctrl_partial_access.1519906623
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2846823628
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2542926042
/workspace/coverage/default/11.sram_ctrl_regwen.2697046115
/workspace/coverage/default/11.sram_ctrl_smoke.1100374225
/workspace/coverage/default/11.sram_ctrl_stress_all.3181745681
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.1332289994
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/workspace/coverage/default/42.sram_ctrl_smoke.2942683166
/workspace/coverage/default/42.sram_ctrl_stress_all.3341073676
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.850230196
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.853155164
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.2804898737
/workspace/coverage/default/43.sram_ctrl_alert_test.2042586153
/workspace/coverage/default/43.sram_ctrl_bijection.1294415405
/workspace/coverage/default/43.sram_ctrl_executable.1771292408
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3147743435
/workspace/coverage/default/43.sram_ctrl_max_throughput.392858065
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.1401938025
/workspace/coverage/default/43.sram_ctrl_mem_walk.3281334449
/workspace/coverage/default/43.sram_ctrl_multiple_keys.951513845
/workspace/coverage/default/43.sram_ctrl_partial_access.4211369806
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3663885891
/workspace/coverage/default/43.sram_ctrl_ram_cfg.4080613995
/workspace/coverage/default/43.sram_ctrl_regwen.2928562238
/workspace/coverage/default/43.sram_ctrl_smoke.1766917616
/workspace/coverage/default/43.sram_ctrl_stress_all.2811610555
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2723263453
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.1305113305
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1044921199
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.1689560804
/workspace/coverage/default/44.sram_ctrl_alert_test.1953168089
/workspace/coverage/default/44.sram_ctrl_bijection.4292064273
/workspace/coverage/default/44.sram_ctrl_executable.2264347092
/workspace/coverage/default/44.sram_ctrl_lc_escalation.2106882434
/workspace/coverage/default/44.sram_ctrl_max_throughput.446889863
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.1668434880
/workspace/coverage/default/44.sram_ctrl_mem_walk.4165443570
/workspace/coverage/default/44.sram_ctrl_multiple_keys.44606664
/workspace/coverage/default/44.sram_ctrl_partial_access.1465029275
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1310650331
/workspace/coverage/default/44.sram_ctrl_ram_cfg.660489045
/workspace/coverage/default/44.sram_ctrl_regwen.1299790123
/workspace/coverage/default/44.sram_ctrl_smoke.3263877452
/workspace/coverage/default/44.sram_ctrl_stress_all.4282695719
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3369741248
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.4231304978
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.946067451
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3993732306
/workspace/coverage/default/45.sram_ctrl_alert_test.3950115166
/workspace/coverage/default/45.sram_ctrl_bijection.70670405
/workspace/coverage/default/45.sram_ctrl_executable.2305699720
/workspace/coverage/default/45.sram_ctrl_lc_escalation.4101320540
/workspace/coverage/default/45.sram_ctrl_max_throughput.333606159
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.365305967
/workspace/coverage/default/45.sram_ctrl_mem_walk.3743973117
/workspace/coverage/default/45.sram_ctrl_multiple_keys.1073822336
/workspace/coverage/default/45.sram_ctrl_partial_access.1232374320
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3672306058
/workspace/coverage/default/45.sram_ctrl_ram_cfg.3034583894
/workspace/coverage/default/45.sram_ctrl_regwen.4143771932
/workspace/coverage/default/45.sram_ctrl_smoke.3066452738
/workspace/coverage/default/45.sram_ctrl_stress_all.1467521659
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.591199401
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3403496524
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.326939007
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.729656260
/workspace/coverage/default/46.sram_ctrl_alert_test.1629140937
/workspace/coverage/default/46.sram_ctrl_bijection.1514370044
/workspace/coverage/default/46.sram_ctrl_executable.1852420705
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1069539491
/workspace/coverage/default/46.sram_ctrl_max_throughput.1281552947
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.2811249165
/workspace/coverage/default/46.sram_ctrl_mem_walk.929449033
/workspace/coverage/default/46.sram_ctrl_multiple_keys.639606522
/workspace/coverage/default/46.sram_ctrl_partial_access.2167486779
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2617079072
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3107724603
/workspace/coverage/default/46.sram_ctrl_regwen.860394696
/workspace/coverage/default/46.sram_ctrl_smoke.2064281560
/workspace/coverage/default/46.sram_ctrl_stress_all.609903021
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2430367546
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3431995154
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.411607438
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.3972581431
/workspace/coverage/default/47.sram_ctrl_alert_test.3142948824
/workspace/coverage/default/47.sram_ctrl_bijection.1968334034
/workspace/coverage/default/47.sram_ctrl_executable.971997466
/workspace/coverage/default/47.sram_ctrl_lc_escalation.3466543545
/workspace/coverage/default/47.sram_ctrl_max_throughput.2952311378
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1132135753
/workspace/coverage/default/47.sram_ctrl_mem_walk.3749408674
/workspace/coverage/default/47.sram_ctrl_multiple_keys.2184678869
/workspace/coverage/default/47.sram_ctrl_partial_access.465389277
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.426824367
/workspace/coverage/default/47.sram_ctrl_ram_cfg.201817884
/workspace/coverage/default/47.sram_ctrl_regwen.2183170361
/workspace/coverage/default/47.sram_ctrl_smoke.1780975265
/workspace/coverage/default/47.sram_ctrl_stress_all.4038121089
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.222647928
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.2050453016
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2217964505
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.228329919
/workspace/coverage/default/48.sram_ctrl_alert_test.1021027477
/workspace/coverage/default/48.sram_ctrl_bijection.1848671329
/workspace/coverage/default/48.sram_ctrl_executable.3125501442
/workspace/coverage/default/48.sram_ctrl_lc_escalation.319664979
/workspace/coverage/default/48.sram_ctrl_max_throughput.2514567619
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.3642235846
/workspace/coverage/default/48.sram_ctrl_mem_walk.3104855873
/workspace/coverage/default/48.sram_ctrl_multiple_keys.3662924317
/workspace/coverage/default/48.sram_ctrl_partial_access.3292776917
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2164134901
/workspace/coverage/default/48.sram_ctrl_ram_cfg.2537946264
/workspace/coverage/default/48.sram_ctrl_regwen.1013368003
/workspace/coverage/default/48.sram_ctrl_smoke.715920111
/workspace/coverage/default/48.sram_ctrl_stress_all.3078439176
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.717040761
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.4281967580
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3602855284
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2775454202
/workspace/coverage/default/49.sram_ctrl_alert_test.2878270915
/workspace/coverage/default/49.sram_ctrl_bijection.2460474471
/workspace/coverage/default/49.sram_ctrl_executable.3785316442
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2014773816
/workspace/coverage/default/49.sram_ctrl_max_throughput.1166191094
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3380511420
/workspace/coverage/default/49.sram_ctrl_mem_walk.403543622
/workspace/coverage/default/49.sram_ctrl_multiple_keys.3306606299
/workspace/coverage/default/49.sram_ctrl_partial_access.3328588856
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.595675083
/workspace/coverage/default/49.sram_ctrl_ram_cfg.3387153786
/workspace/coverage/default/49.sram_ctrl_regwen.931150146
/workspace/coverage/default/49.sram_ctrl_smoke.879742780
/workspace/coverage/default/49.sram_ctrl_stress_all.1931117869
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3559328290
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2467328657
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.962142725
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.4011383637
/workspace/coverage/default/5.sram_ctrl_alert_test.2930690912
/workspace/coverage/default/5.sram_ctrl_bijection.2149783525
/workspace/coverage/default/5.sram_ctrl_executable.3973397201
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2840786627
/workspace/coverage/default/5.sram_ctrl_max_throughput.1853955723
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.4289856073
/workspace/coverage/default/5.sram_ctrl_mem_walk.3220695387
/workspace/coverage/default/5.sram_ctrl_multiple_keys.404350771
/workspace/coverage/default/5.sram_ctrl_partial_access.3797980836
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.876912392
/workspace/coverage/default/5.sram_ctrl_ram_cfg.1823150641
/workspace/coverage/default/5.sram_ctrl_regwen.673082632
/workspace/coverage/default/5.sram_ctrl_smoke.1596783657
/workspace/coverage/default/5.sram_ctrl_stress_all.3799389646
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3963604485
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.66393274
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3414927499
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2146961399
/workspace/coverage/default/6.sram_ctrl_alert_test.4203229037
/workspace/coverage/default/6.sram_ctrl_bijection.1748957010
/workspace/coverage/default/6.sram_ctrl_executable.2526009963
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2659339414
/workspace/coverage/default/6.sram_ctrl_max_throughput.1470730355
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.873035072
/workspace/coverage/default/6.sram_ctrl_mem_walk.1860150520
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1398984238
/workspace/coverage/default/6.sram_ctrl_partial_access.3635079727
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1508205387
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2573350968
/workspace/coverage/default/6.sram_ctrl_regwen.1810407196
/workspace/coverage/default/6.sram_ctrl_smoke.212823369
/workspace/coverage/default/6.sram_ctrl_stress_all.2632574858
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.15052432
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3247448554
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.891984023
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.3380767099
/workspace/coverage/default/7.sram_ctrl_alert_test.1393396867
/workspace/coverage/default/7.sram_ctrl_bijection.618342769
/workspace/coverage/default/7.sram_ctrl_executable.1423157943
/workspace/coverage/default/7.sram_ctrl_lc_escalation.1447548217
/workspace/coverage/default/7.sram_ctrl_max_throughput.4189339569
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.972253061
/workspace/coverage/default/7.sram_ctrl_mem_walk.2977067469
/workspace/coverage/default/7.sram_ctrl_multiple_keys.84434302
/workspace/coverage/default/7.sram_ctrl_partial_access.3191605909
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2340953663
/workspace/coverage/default/7.sram_ctrl_ram_cfg.3404670205
/workspace/coverage/default/7.sram_ctrl_regwen.3812436743
/workspace/coverage/default/7.sram_ctrl_smoke.1036824931
/workspace/coverage/default/7.sram_ctrl_stress_all.3966665804
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1776113629
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.4253323230
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.53843819
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1850089262
/workspace/coverage/default/8.sram_ctrl_alert_test.2144267477
/workspace/coverage/default/8.sram_ctrl_bijection.300954662
/workspace/coverage/default/8.sram_ctrl_executable.2170933774
/workspace/coverage/default/8.sram_ctrl_lc_escalation.2302905210
/workspace/coverage/default/8.sram_ctrl_max_throughput.370617354
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.2802948000
/workspace/coverage/default/8.sram_ctrl_mem_walk.4045110372
/workspace/coverage/default/8.sram_ctrl_multiple_keys.1706141197
/workspace/coverage/default/8.sram_ctrl_partial_access.2450365467
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1844240939
/workspace/coverage/default/8.sram_ctrl_ram_cfg.2992556426
/workspace/coverage/default/8.sram_ctrl_regwen.2158716327
/workspace/coverage/default/8.sram_ctrl_smoke.3808437329
/workspace/coverage/default/8.sram_ctrl_stress_all.3234819639
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3210073578
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.728424943
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1511792948
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1363985507
/workspace/coverage/default/9.sram_ctrl_alert_test.4189333919
/workspace/coverage/default/9.sram_ctrl_bijection.2616818064
/workspace/coverage/default/9.sram_ctrl_executable.1584937794
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3243484013
/workspace/coverage/default/9.sram_ctrl_max_throughput.2165734121
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2023174269
/workspace/coverage/default/9.sram_ctrl_mem_walk.4286534282
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3068368666
/workspace/coverage/default/9.sram_ctrl_partial_access.425247032
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2380101484
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3397339907
/workspace/coverage/default/9.sram_ctrl_regwen.156139293
/workspace/coverage/default/9.sram_ctrl_smoke.1399070741
/workspace/coverage/default/9.sram_ctrl_stress_all.2964382636
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2182150982
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.2474099979
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3460470235

Total test records in report: 1033

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/31.sram_ctrl_mem_walk.2621589903	May 05 02:02:46 PM PDT 24	May 05 02:02:51 PM PDT 24	75350783 ps
T2	/workspace/coverage/default/19.sram_ctrl_partial_access.567586675	May 05 02:00:18 PM PDT 24	May 05 02:00:23 PM PDT 24	191213073 ps
T3	/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.4228792042	May 05 02:00:01 PM PDT 24	May 05 02:03:54 PM PDT 24	12962210840 ps
T4	/workspace/coverage/default/2.sram_ctrl_multiple_keys.1240649960	May 05 01:58:30 PM PDT 24	May 05 02:20:15 PM PDT 24	14413937315 ps
T6	/workspace/coverage/default/30.sram_ctrl_smoke.2409784007	May 05 02:02:25 PM PDT 24	May 05 02:02:33 PM PDT 24	314409311 ps
T5	/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.595675083	May 05 02:06:53 PM PDT 24	May 05 02:10:35 PM PDT 24	87309174877 ps
T11	/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.946067451	May 05 02:05:48 PM PDT 24	May 05 02:06:05 PM PDT 24	87345030 ps
T12	/workspace/coverage/default/33.sram_ctrl_alert_test.2963485752	May 05 02:03:16 PM PDT 24	May 05 02:03:18 PM PDT 24	42101276 ps
T13	/workspace/coverage/default/25.sram_ctrl_regwen.2691580437	May 05 02:01:26 PM PDT 24	May 05 02:13:56 PM PDT 24	10370414872 ps
T14	/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.1242188570	May 05 02:02:04 PM PDT 24	May 05 02:03:36 PM PDT 24	1159915598 ps
T17	/workspace/coverage/default/41.sram_ctrl_multiple_keys.1511453148	May 05 02:04:57 PM PDT 24	May 05 02:06:18 PM PDT 24	5239228914 ps
T20	/workspace/coverage/default/29.sram_ctrl_ram_cfg.1069016624	May 05 02:02:22 PM PDT 24	May 05 02:02:23 PM PDT 24	28356237 ps
T23	/workspace/coverage/default/37.sram_ctrl_alert_test.684718849	May 05 02:04:09 PM PDT 24	May 05 02:04:10 PM PDT 24	36285475 ps
T18	/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.511618428	May 05 02:05:06 PM PDT 24	May 05 02:05:39 PM PDT 24	1127825480 ps
T19	/workspace/coverage/default/40.sram_ctrl_regwen.3515792902	May 05 02:04:47 PM PDT 24	May 05 02:21:09 PM PDT 24	59575423193 ps
T52	/workspace/coverage/default/39.sram_ctrl_stress_pipeline.86764394	May 05 02:04:30 PM PDT 24	May 05 02:07:05 PM PDT 24	3425672782 ps
T16	/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.409442061	May 05 02:04:09 PM PDT 24	May 05 02:07:43 PM PDT 24	2337036132 ps
T15	/workspace/coverage/default/42.sram_ctrl_multiple_keys.3346416995	May 05 02:05:11 PM PDT 24	May 05 02:20:33 PM PDT 24	32502304838 ps
T30	/workspace/coverage/default/24.sram_ctrl_ram_cfg.3762305740	May 05 02:01:17 PM PDT 24	May 05 02:01:19 PM PDT 24	25872787 ps
T7	/workspace/coverage/default/28.sram_ctrl_stress_all.2717974528	May 05 02:02:07 PM PDT 24	May 05 03:00:06 PM PDT 24	53695234804 ps
T41	/workspace/coverage/default/20.sram_ctrl_access_during_key_req.2223898040	May 05 02:00:27 PM PDT 24	May 05 02:00:45 PM PDT 24	271121131 ps
T53	/workspace/coverage/default/3.sram_ctrl_bijection.1283069452	May 05 01:58:43 PM PDT 24	May 05 01:59:18 PM PDT 24	4548517147 ps
T10	/workspace/coverage/default/2.sram_ctrl_sec_cm.728105249	May 05 01:58:35 PM PDT 24	May 05 01:58:39 PM PDT 24	436975306 ps
T34	/workspace/coverage/default/33.sram_ctrl_smoke.1871923482	May 05 02:03:11 PM PDT 24	May 05 02:03:29 PM PDT 24	3600393901 ps
T35	/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2617079072	May 05 02:06:11 PM PDT 24	May 05 02:12:55 PM PDT 24	16560992204 ps
T36	/workspace/coverage/default/29.sram_ctrl_executable.3378542701	May 05 02:02:18 PM PDT 24	May 05 02:24:03 PM PDT 24	4103145081 ps
T8	/workspace/coverage/default/46.sram_ctrl_lc_escalation.1069539491	May 05 02:06:13 PM PDT 24	May 05 02:06:19 PM PDT 24	1205370724 ps
T37	/workspace/coverage/default/37.sram_ctrl_mem_walk.3768871434	May 05 02:04:10 PM PDT 24	May 05 02:04:19 PM PDT 24	594807961 ps
T38	/workspace/coverage/default/3.sram_ctrl_mem_partial_access.1691543031	May 05 01:58:40 PM PDT 24	May 05 01:58:45 PM PDT 24	111142424 ps
T39	/workspace/coverage/default/18.sram_ctrl_access_during_key_req.1996249308	May 05 02:00:12 PM PDT 24	May 05 02:06:41 PM PDT 24	1234706981 ps
T40	/workspace/coverage/default/42.sram_ctrl_smoke.2942683166	May 05 02:05:10 PM PDT 24	May 05 02:06:09 PM PDT 24	437125422 ps
T31	/workspace/coverage/default/4.sram_ctrl_ram_cfg.1992217117	May 05 01:58:45 PM PDT 24	May 05 01:58:46 PM PDT 24	61607577 ps
T26	/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1697904016	May 05 02:04:30 PM PDT 24	May 05 02:10:26 PM PDT 24	8401559216 ps
T27	/workspace/coverage/default/0.sram_ctrl_regwen.309972255	May 05 01:58:22 PM PDT 24	May 05 02:05:28 PM PDT 24	3939605245 ps
T138	/workspace/coverage/default/40.sram_ctrl_mem_walk.1025833005	May 05 02:04:54 PM PDT 24	May 05 02:05:02 PM PDT 24	137153389 ps
T25	/workspace/coverage/default/6.sram_ctrl_lc_escalation.2659339414	May 05 01:58:54 PM PDT 24	May 05 01:58:56 PM PDT 24	447709342 ps
T24	/workspace/coverage/default/26.sram_ctrl_alert_test.333645814	May 05 02:01:41 PM PDT 24	May 05 02:01:42 PM PDT 24	77515493 ps
T42	/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2775454202	May 05 02:06:57 PM PDT 24	May 05 02:24:06 PM PDT 24	3826725183 ps
T43	/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3788072481	May 05 02:00:28 PM PDT 24	May 05 02:06:05 PM PDT 24	6659825214 ps
T139	/workspace/coverage/default/5.sram_ctrl_ram_cfg.1823150641	May 05 01:58:49 PM PDT 24	May 05 01:58:50 PM PDT 24	28377093 ps
T140	/workspace/coverage/default/41.sram_ctrl_alert_test.2336011037	May 05 02:05:12 PM PDT 24	May 05 02:05:12 PM PDT 24	40746263 ps
T137	/workspace/coverage/default/8.sram_ctrl_partial_access.2450365467	May 05 01:59:03 PM PDT 24	May 05 01:59:12 PM PDT 24	678702012 ps
T89	/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3403496524	May 05 02:05:58 PM PDT 24	May 05 02:09:32 PM PDT 24	2422320025 ps
T141	/workspace/coverage/default/7.sram_ctrl_max_throughput.4189339569	May 05 01:58:53 PM PDT 24	May 05 01:59:10 PM PDT 24	70793373 ps
T142	/workspace/coverage/default/31.sram_ctrl_partial_access.643560374	May 05 02:02:42 PM PDT 24	May 05 02:02:59 PM PDT 24	1421624219 ps
T143	/workspace/coverage/default/26.sram_ctrl_multiple_keys.1848263437	May 05 02:01:32 PM PDT 24	May 05 02:12:01 PM PDT 24	8468627086 ps
T144	/workspace/coverage/default/41.sram_ctrl_ram_cfg.650211844	May 05 02:05:03 PM PDT 24	May 05 02:05:04 PM PDT 24	108477134 ps
T68	/workspace/coverage/default/33.sram_ctrl_access_during_key_req.4116226293	May 05 02:03:17 PM PDT 24	May 05 02:09:56 PM PDT 24	3487419233 ps
T90	/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1646703627	May 05 01:58:30 PM PDT 24	May 05 02:02:45 PM PDT 24	14572637465 ps
T145	/workspace/coverage/default/33.sram_ctrl_bijection.4079824826	May 05 02:03:11 PM PDT 24	May 05 02:03:26 PM PDT 24	783920888 ps
T44	/workspace/coverage/default/44.sram_ctrl_stress_all.4282695719	May 05 02:05:58 PM PDT 24	May 05 02:51:49 PM PDT 24	51145206531 ps
T9	/workspace/coverage/default/1.sram_ctrl_lc_escalation.3011000415	May 05 01:58:27 PM PDT 24	May 05 01:58:31 PM PDT 24	291782338 ps
T54	/workspace/coverage/default/1.sram_ctrl_regwen.1383477907	May 05 01:58:30 PM PDT 24	May 05 02:13:31 PM PDT 24	2880732009 ps
T146	/workspace/coverage/default/25.sram_ctrl_multiple_keys.1255782520	May 05 02:01:17 PM PDT 24	May 05 02:18:35 PM PDT 24	15174627817 ps
T69	/workspace/coverage/default/35.sram_ctrl_mem_partial_access.2327246840	May 05 02:03:46 PM PDT 24	May 05 02:03:50 PM PDT 24	671493637 ps
T147	/workspace/coverage/default/47.sram_ctrl_smoke.1780975265	May 05 02:06:16 PM PDT 24	May 05 02:07:35 PM PDT 24	137983222 ps
T148	/workspace/coverage/default/5.sram_ctrl_alert_test.2930690912	May 05 01:58:51 PM PDT 24	May 05 01:58:52 PM PDT 24	18159022 ps
T149	/workspace/coverage/default/34.sram_ctrl_mem_walk.2711289624	May 05 02:03:30 PM PDT 24	May 05 02:03:41 PM PDT 24	467237468 ps
T150	/workspace/coverage/default/17.sram_ctrl_multiple_keys.700809448	May 05 01:59:55 PM PDT 24	May 05 02:17:21 PM PDT 24	18059780779 ps
T91	/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.3996409163	May 05 02:01:05 PM PDT 24	May 05 02:04:08 PM PDT 24	2890732201 ps
T55	/workspace/coverage/default/29.sram_ctrl_stress_all.200781223	May 05 02:02:25 PM PDT 24	May 05 03:14:38 PM PDT 24	205153691825 ps
T151	/workspace/coverage/default/46.sram_ctrl_max_throughput.1281552947	May 05 02:06:13 PM PDT 24	May 05 02:06:29 PM PDT 24	72107580 ps
T92	/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3663885891	May 05 02:05:30 PM PDT 24	May 05 02:09:42 PM PDT 24	19035360708 ps
T152	/workspace/coverage/default/27.sram_ctrl_max_throughput.4222419655	May 05 02:01:48 PM PDT 24	May 05 02:02:32 PM PDT 24	99300876 ps
T153	/workspace/coverage/default/15.sram_ctrl_stress_pipeline.3533709295	May 05 01:59:41 PM PDT 24	May 05 02:03:03 PM PDT 24	12757140466 ps
T154	/workspace/coverage/default/31.sram_ctrl_ram_cfg.1411385840	May 05 02:02:46 PM PDT 24	May 05 02:02:47 PM PDT 24	47359904 ps
T155	/workspace/coverage/default/25.sram_ctrl_alert_test.843771036	May 05 02:01:31 PM PDT 24	May 05 02:01:32 PM PDT 24	29356322 ps
T156	/workspace/coverage/default/32.sram_ctrl_stress_pipeline.1607090291	May 05 02:02:59 PM PDT 24	May 05 02:06:34 PM PDT 24	2396704405 ps
T70	/workspace/coverage/default/23.sram_ctrl_mem_partial_access.4017058249	May 05 02:01:06 PM PDT 24	May 05 02:01:10 PM PDT 24	251340207 ps
T157	/workspace/coverage/default/12.sram_ctrl_alert_test.1790352428	May 05 01:59:26 PM PDT 24	May 05 01:59:27 PM PDT 24	45457592 ps
T158	/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.853155164	May 05 02:05:14 PM PDT 24	May 05 02:07:05 PM PDT 24	859165618 ps
T159	/workspace/coverage/default/26.sram_ctrl_stress_pipeline.2544224556	May 05 02:01:38 PM PDT 24	May 05 02:03:44 PM PDT 24	1405626681 ps
T71	/workspace/coverage/default/2.sram_ctrl_access_during_key_req.3563562281	May 05 01:58:34 PM PDT 24	May 05 02:06:22 PM PDT 24	4488211891 ps
T160	/workspace/coverage/default/19.sram_ctrl_mem_walk.790113909	May 05 02:00:20 PM PDT 24	May 05 02:00:30 PM PDT 24	654171398 ps
T161	/workspace/coverage/default/30.sram_ctrl_ram_cfg.3928105083	May 05 02:02:32 PM PDT 24	May 05 02:02:33 PM PDT 24	86153285 ps
T45	/workspace/coverage/default/41.sram_ctrl_executable.4058296567	May 05 02:05:03 PM PDT 24	May 05 02:17:28 PM PDT 24	91982980045 ps
T162	/workspace/coverage/default/37.sram_ctrl_regwen.4158759707	May 05 02:04:10 PM PDT 24	May 05 02:18:18 PM PDT 24	10619414887 ps
T163	/workspace/coverage/default/20.sram_ctrl_ram_cfg.1915221668	May 05 02:00:28 PM PDT 24	May 05 02:00:29 PM PDT 24	218867737 ps
T134	/workspace/coverage/default/8.sram_ctrl_regwen.2158716327	May 05 01:59:03 PM PDT 24	May 05 02:14:03 PM PDT 24	18776282656 ps
T164	/workspace/coverage/default/11.sram_ctrl_ram_cfg.2542926042	May 05 01:59:18 PM PDT 24	May 05 01:59:19 PM PDT 24	45644813 ps
T165	/workspace/coverage/default/18.sram_ctrl_executable.427375094	May 05 02:00:15 PM PDT 24	May 05 02:06:03 PM PDT 24	4016992151 ps
T166	/workspace/coverage/default/35.sram_ctrl_stress_pipeline.3650013372	May 05 02:03:43 PM PDT 24	May 05 02:06:50 PM PDT 24	2056419634 ps
T46	/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2535471413	May 05 02:02:54 PM PDT 24	May 05 02:03:00 PM PDT 24	167429764 ps
T167	/workspace/coverage/default/29.sram_ctrl_regwen.1926836790	May 05 02:02:22 PM PDT 24	May 05 02:04:40 PM PDT 24	13595687376 ps
T168	/workspace/coverage/default/7.sram_ctrl_smoke.1036824931	May 05 01:58:54 PM PDT 24	May 05 01:58:58 PM PDT 24	376896412 ps
T169	/workspace/coverage/default/21.sram_ctrl_regwen.3582312561	May 05 02:00:37 PM PDT 24	May 05 02:10:45 PM PDT 24	9370808094 ps
T170	/workspace/coverage/default/1.sram_ctrl_multiple_keys.2756244670	May 05 01:58:25 PM PDT 24	May 05 02:14:48 PM PDT 24	16696661700 ps
T171	/workspace/coverage/default/1.sram_ctrl_stress_pipeline.506907013	May 05 01:58:26 PM PDT 24	May 05 02:00:34 PM PDT 24	2260568204 ps
T172	/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3148887144	May 05 01:59:22 PM PDT 24	May 05 01:59:24 PM PDT 24	425029179 ps
T173	/workspace/coverage/default/17.sram_ctrl_executable.1610818818	May 05 02:00:00 PM PDT 24	May 05 02:09:26 PM PDT 24	8159288361 ps
T174	/workspace/coverage/default/36.sram_ctrl_executable.2597165097	May 05 02:03:50 PM PDT 24	May 05 02:21:29 PM PDT 24	36085138128 ps
T175	/workspace/coverage/default/19.sram_ctrl_smoke.3781418075	May 05 02:00:14 PM PDT 24	May 05 02:00:28 PM PDT 24	243201518 ps
T72	/workspace/coverage/default/16.sram_ctrl_mem_partial_access.158052337	May 05 01:59:51 PM PDT 24	May 05 01:59:54 PM PDT 24	400322125 ps
T73	/workspace/coverage/default/0.sram_ctrl_mem_partial_access.2400157752	May 05 01:58:26 PM PDT 24	May 05 01:58:32 PM PDT 24	297769699 ps
T176	/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3854978090	May 05 01:58:27 PM PDT 24	May 05 01:58:43 PM PDT 24	151729145 ps
T177	/workspace/coverage/default/8.sram_ctrl_max_throughput.370617354	May 05 01:59:05 PM PDT 24	May 05 01:59:39 PM PDT 24	193175971 ps
T178	/workspace/coverage/default/21.sram_ctrl_partial_access.2334487468	May 05 02:00:37 PM PDT 24	May 05 02:00:56 PM PDT 24	1979100729 ps
T179	/workspace/coverage/default/24.sram_ctrl_smoke.2579320456	May 05 02:01:06 PM PDT 24	May 05 02:01:21 PM PDT 24	456531444 ps
T180	/workspace/coverage/default/37.sram_ctrl_bijection.2435053791	May 05 02:04:00 PM PDT 24	May 05 02:04:28 PM PDT 24	12423088536 ps
T47	/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3765859672	May 05 02:01:45 PM PDT 24	May 05 02:19:12 PM PDT 24	11061269154 ps
T181	/workspace/coverage/default/47.sram_ctrl_bijection.1968334034	May 05 02:06:20 PM PDT 24	May 05 02:07:28 PM PDT 24	3032391941 ps
T133	/workspace/coverage/default/25.sram_ctrl_executable.1245241515	May 05 02:01:29 PM PDT 24	May 05 02:06:24 PM PDT 24	4661960701 ps
T182	/workspace/coverage/default/35.sram_ctrl_executable.2524443718	May 05 02:03:44 PM PDT 24	May 05 02:06:12 PM PDT 24	4350476238 ps
T135	/workspace/coverage/default/37.sram_ctrl_stress_all.3608641500	May 05 02:04:09 PM PDT 24	May 05 03:12:07 PM PDT 24	317539707973 ps
T117	/workspace/coverage/default/24.sram_ctrl_lc_escalation.3327779492	May 05 02:01:11 PM PDT 24	May 05 02:01:19 PM PDT 24	2535268124 ps
T183	/workspace/coverage/default/13.sram_ctrl_partial_access.4040107124	May 05 01:59:27 PM PDT 24	May 05 01:59:59 PM PDT 24	146491745 ps
T184	/workspace/coverage/default/14.sram_ctrl_alert_test.3537243548	May 05 01:59:42 PM PDT 24	May 05 01:59:43 PM PDT 24	34765259 ps
T185	/workspace/coverage/default/2.sram_ctrl_mem_walk.3111879862	May 05 01:58:36 PM PDT 24	May 05 01:58:44 PM PDT 24	140862823 ps
T186	/workspace/coverage/default/7.sram_ctrl_ram_cfg.3404670205	May 05 01:59:01 PM PDT 24	May 05 01:59:02 PM PDT 24	82200700 ps
T48	/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3310182323	May 05 02:01:19 PM PDT 24	May 05 02:02:25 PM PDT 24	2967449614 ps
T187	/workspace/coverage/default/48.sram_ctrl_multiple_keys.3662924317	May 05 02:06:39 PM PDT 24	May 05 02:28:19 PM PDT 24	15883192389 ps
T188	/workspace/coverage/default/42.sram_ctrl_partial_access.2404959753	May 05 02:05:14 PM PDT 24	May 05 02:05:26 PM PDT 24	1227277439 ps
T189	/workspace/coverage/default/31.sram_ctrl_mem_partial_access.2070354768	May 05 02:02:46 PM PDT 24	May 05 02:02:49 PM PDT 24	85414626 ps
T190	/workspace/coverage/default/42.sram_ctrl_mem_walk.4013454679	May 05 02:05:19 PM PDT 24	May 05 02:05:25 PM PDT 24	230853900 ps
T191	/workspace/coverage/default/8.sram_ctrl_executable.2170933774	May 05 01:59:05 PM PDT 24	May 05 02:02:25 PM PDT 24	1708497157 ps
T192	/workspace/coverage/default/3.sram_ctrl_multiple_keys.3203553320	May 05 01:58:38 PM PDT 24	May 05 02:13:08 PM PDT 24	4654757934 ps
T193	/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2146961399	May 05 01:58:54 PM PDT 24	May 05 02:01:33 PM PDT 24	2251531995 ps
T194	/workspace/coverage/default/36.sram_ctrl_bijection.2468319704	May 05 02:03:46 PM PDT 24	May 05 02:04:12 PM PDT 24	5209438485 ps
T195	/workspace/coverage/default/28.sram_ctrl_regwen.526073034	May 05 02:02:01 PM PDT 24	May 05 02:09:04 PM PDT 24	1693727538 ps
T196	/workspace/coverage/default/3.sram_ctrl_regwen.2065390636	May 05 01:58:40 PM PDT 24	May 05 02:10:57 PM PDT 24	36379302065 ps
T197	/workspace/coverage/default/23.sram_ctrl_multiple_keys.986060397	May 05 02:00:56 PM PDT 24	May 05 02:12:12 PM PDT 24	6886512951 ps
T198	/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2467328657	May 05 02:06:49 PM PDT 24	May 05 02:10:38 PM PDT 24	2680662061 ps
T199	/workspace/coverage/default/36.sram_ctrl_mem_partial_access.2753431377	May 05 02:03:54 PM PDT 24	May 05 02:03:59 PM PDT 24	63723275 ps
T200	/workspace/coverage/default/4.sram_ctrl_multiple_keys.2422229827	May 05 01:58:44 PM PDT 24	May 05 02:05:42 PM PDT 24	1953223083 ps
T201	/workspace/coverage/default/10.sram_ctrl_bijection.3003838541	May 05 01:59:12 PM PDT 24	May 05 02:00:14 PM PDT 24	1312907359 ps
T202	/workspace/coverage/default/21.sram_ctrl_ram_cfg.530652528	May 05 02:00:41 PM PDT 24	May 05 02:00:43 PM PDT 24	30514667 ps
T203	/workspace/coverage/default/12.sram_ctrl_mem_partial_access.3577800363	May 05 01:59:26 PM PDT 24	May 05 01:59:29 PM PDT 24	153083074 ps
T204	/workspace/coverage/default/5.sram_ctrl_stress_all.3799389646	May 05 01:58:48 PM PDT 24	May 05 02:32:38 PM PDT 24	7833230630 ps
T205	/workspace/coverage/default/27.sram_ctrl_regwen.2028717701	May 05 02:01:52 PM PDT 24	May 05 02:11:54 PM PDT 24	4420789474 ps
T206	/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.133288427	May 05 02:03:51 PM PDT 24	May 05 02:05:29 PM PDT 24	278867316 ps
T207	/workspace/coverage/default/35.sram_ctrl_max_throughput.3524647846	May 05 02:03:44 PM PDT 24	May 05 02:03:54 PM PDT 24	280514313 ps
T208	/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1168561694	May 05 02:03:11 PM PDT 24	May 05 02:11:23 PM PDT 24	19860797597 ps
T209	/workspace/coverage/default/28.sram_ctrl_access_during_key_req.3980211669	May 05 02:02:03 PM PDT 24	May 05 02:15:10 PM PDT 24	3630771498 ps
T210	/workspace/coverage/default/18.sram_ctrl_regwen.2885375370	May 05 02:00:14 PM PDT 24	May 05 02:02:37 PM PDT 24	4357354581 ps
T211	/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1044921199	May 05 02:05:29 PM PDT 24	May 05 02:06:13 PM PDT 24	472291055 ps
T21	/workspace/coverage/default/1.sram_ctrl_sec_cm.4284292012	May 05 01:58:29 PM PDT 24	May 05 01:58:32 PM PDT 24	137951492 ps
T118	/workspace/coverage/default/48.sram_ctrl_stress_all.3078439176	May 05 02:06:46 PM PDT 24	May 05 02:49:45 PM PDT 24	182923562851 ps
T212	/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3538134042	May 05 02:02:56 PM PDT 24	May 05 02:08:16 PM PDT 24	12282644327 ps
T213	/workspace/coverage/default/9.sram_ctrl_mem_walk.4286534282	May 05 01:59:09 PM PDT 24	May 05 01:59:15 PM PDT 24	2048120409 ps
T214	/workspace/coverage/default/22.sram_ctrl_stress_pipeline.1481142770	May 05 02:00:46 PM PDT 24	May 05 02:06:42 PM PDT 24	14931483221 ps
T215	/workspace/coverage/default/37.sram_ctrl_executable.858726262	May 05 02:04:06 PM PDT 24	May 05 02:13:17 PM PDT 24	34758111609 ps
T216	/workspace/coverage/default/26.sram_ctrl_partial_access.3388700342	May 05 02:01:37 PM PDT 24	May 05 02:01:49 PM PDT 24	680127348 ps
T217	/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1508205387	May 05 01:58:48 PM PDT 24	May 05 02:02:35 PM PDT 24	27314205268 ps
T218	/workspace/coverage/default/14.sram_ctrl_bijection.51846038	May 05 01:59:36 PM PDT 24	May 05 02:00:59 PM PDT 24	25940287188 ps
T219	/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3993732306	May 05 02:06:01 PM PDT 24	May 05 02:17:54 PM PDT 24	3229906738 ps
T220	/workspace/coverage/default/8.sram_ctrl_mem_walk.4045110372	May 05 01:59:04 PM PDT 24	May 05 01:59:14 PM PDT 24	660388845 ps
T221	/workspace/coverage/default/11.sram_ctrl_executable.1596203297	May 05 01:59:17 PM PDT 24	May 05 02:15:01 PM PDT 24	11028462311 ps
T222	/workspace/coverage/default/40.sram_ctrl_stress_all.4263148065	May 05 02:04:52 PM PDT 24	May 05 02:38:58 PM PDT 24	121181061983 ps
T223	/workspace/coverage/default/45.sram_ctrl_alert_test.3950115166	May 05 02:06:07 PM PDT 24	May 05 02:06:08 PM PDT 24	13313308 ps
T49	/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2066053079	May 05 02:04:54 PM PDT 24	May 05 02:05:15 PM PDT 24	3369025455 ps
T108	/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1511792948	May 05 01:59:04 PM PDT 24	May 05 01:59:54 PM PDT 24	255432222 ps
T109	/workspace/coverage/default/32.sram_ctrl_smoke.4127092231	May 05 02:02:53 PM PDT 24	May 05 02:03:04 PM PDT 24	669383122 ps
T110	/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.460542431	May 05 02:01:37 PM PDT 24	May 05 02:01:57 PM PDT 24	270797105 ps
T111	/workspace/coverage/default/25.sram_ctrl_smoke.3097381148	May 05 02:01:18 PM PDT 24	May 05 02:01:31 PM PDT 24	1230891964 ps
T112	/workspace/coverage/default/11.sram_ctrl_multiple_keys.3227053666	May 05 01:59:22 PM PDT 24	May 05 02:12:15 PM PDT 24	67854871884 ps
T113	/workspace/coverage/default/1.sram_ctrl_max_throughput.2106342550	May 05 01:58:26 PM PDT 24	May 05 01:58:32 PM PDT 24	98493161 ps
T114	/workspace/coverage/default/16.sram_ctrl_bijection.1263162841	May 05 01:59:46 PM PDT 24	May 05 02:00:22 PM PDT 24	852898452 ps
T115	/workspace/coverage/default/35.sram_ctrl_smoke.247083519	May 05 02:03:45 PM PDT 24	May 05 02:05:03 PM PDT 24	142810130 ps
T116	/workspace/coverage/default/33.sram_ctrl_multiple_keys.2518999880	May 05 02:03:09 PM PDT 24	May 05 02:12:01 PM PDT 24	57968489787 ps
T224	/workspace/coverage/default/34.sram_ctrl_lc_escalation.1219904858	May 05 02:03:24 PM PDT 24	May 05 02:03:31 PM PDT 24	1159115581 ps
T225	/workspace/coverage/default/1.sram_ctrl_partial_access.1554390535	May 05 01:58:26 PM PDT 24	May 05 01:58:59 PM PDT 24	548182238 ps
T226	/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.125884272	May 05 02:04:19 PM PDT 24	May 05 02:04:54 PM PDT 24	108621485 ps
T227	/workspace/coverage/default/31.sram_ctrl_stress_pipeline.2164251322	May 05 02:02:41 PM PDT 24	May 05 02:05:44 PM PDT 24	2025603497 ps
T228	/workspace/coverage/default/18.sram_ctrl_max_throughput.3988623907	May 05 02:00:09 PM PDT 24	May 05 02:00:11 PM PDT 24	345731655 ps
T229	/workspace/coverage/default/39.sram_ctrl_smoke.939820278	May 05 02:04:24 PM PDT 24	May 05 02:04:36 PM PDT 24	774587458 ps
T230	/workspace/coverage/default/34.sram_ctrl_bijection.186259470	May 05 02:03:18 PM PDT 24	May 05 02:03:48 PM PDT 24	3708309376 ps
T231	/workspace/coverage/default/5.sram_ctrl_executable.3973397201	May 05 01:58:54 PM PDT 24	May 05 02:10:52 PM PDT 24	36638925203 ps
T232	/workspace/coverage/default/12.sram_ctrl_stress_all.4183895909	May 05 01:59:27 PM PDT 24	May 05 02:28:49 PM PDT 24	26595058038 ps
T233	/workspace/coverage/default/10.sram_ctrl_multiple_keys.3746365198	May 05 01:59:14 PM PDT 24	May 05 02:13:40 PM PDT 24	3554742511 ps
T234	/workspace/coverage/default/28.sram_ctrl_stress_pipeline.3150908504	May 05 02:01:57 PM PDT 24	May 05 02:05:29 PM PDT 24	8778394749 ps
T235	/workspace/coverage/default/19.sram_ctrl_lc_escalation.3173855618	May 05 02:00:17 PM PDT 24	May 05 02:00:21 PM PDT 24	234495051 ps
T236	/workspace/coverage/default/48.sram_ctrl_alert_test.1021027477	May 05 02:06:44 PM PDT 24	May 05 02:06:45 PM PDT 24	15085113 ps
T237	/workspace/coverage/default/20.sram_ctrl_executable.3623085642	May 05 02:00:29 PM PDT 24	May 05 02:23:10 PM PDT 24	8906806135 ps
T238	/workspace/coverage/default/12.sram_ctrl_partial_access.1278964809	May 05 01:59:23 PM PDT 24	May 05 01:59:39 PM PDT 24	319760970 ps
T239	/workspace/coverage/default/35.sram_ctrl_bijection.2262595174	May 05 02:03:34 PM PDT 24	May 05 02:04:27 PM PDT 24	1671766995 ps
T240	/workspace/coverage/default/18.sram_ctrl_stress_all.2742530917	May 05 02:00:15 PM PDT 24	May 05 02:20:57 PM PDT 24	68787160875 ps
T241	/workspace/coverage/default/45.sram_ctrl_mem_walk.3743973117	May 05 02:06:02 PM PDT 24	May 05 02:06:08 PM PDT 24	1020695207 ps
T242	/workspace/coverage/default/47.sram_ctrl_alert_test.3142948824	May 05 02:06:35 PM PDT 24	May 05 02:06:36 PM PDT 24	22734349 ps
T243	/workspace/coverage/default/16.sram_ctrl_stress_all.2904688021	May 05 01:59:54 PM PDT 24	May 05 02:45:50 PM PDT 24	15990633171 ps
T244	/workspace/coverage/default/19.sram_ctrl_bijection.1624758937	May 05 02:00:19 PM PDT 24	May 05 02:01:17 PM PDT 24	3685498911 ps
T136	/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.2786001170	May 05 02:03:35 PM PDT 24	May 05 02:08:00 PM PDT 24	13342074460 ps
T245	/workspace/coverage/default/3.sram_ctrl_alert_test.4006721455	May 05 01:58:40 PM PDT 24	May 05 01:58:41 PM PDT 24	65268272 ps
T246	/workspace/coverage/default/1.sram_ctrl_mem_partial_access.2209857831	May 05 01:58:29 PM PDT 24	May 05 01:58:32 PM PDT 24	43729344 ps
T247	/workspace/coverage/default/15.sram_ctrl_max_throughput.3049567155	May 05 01:59:46 PM PDT 24	May 05 01:59:55 PM PDT 24	700572031 ps
T248	/workspace/coverage/default/13.sram_ctrl_max_throughput.26435935	May 05 01:59:25 PM PDT 24	May 05 02:00:26 PM PDT 24	266055500 ps
T249	/workspace/coverage/default/41.sram_ctrl_stress_pipeline.2173303267	May 05 02:04:58 PM PDT 24	May 05 02:09:22 PM PDT 24	12887785623 ps
T119	/workspace/coverage/default/27.sram_ctrl_lc_escalation.2372018252	May 05 02:01:51 PM PDT 24	May 05 02:01:53 PM PDT 24	73172964 ps
T250	/workspace/coverage/default/21.sram_ctrl_access_during_key_req.2143835527	May 05 02:00:38 PM PDT 24	May 05 02:20:23 PM PDT 24	3556782657 ps
T251	/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.322601977	May 05 01:58:40 PM PDT 24	May 05 01:58:58 PM PDT 24	82296853 ps
T252	/workspace/coverage/default/23.sram_ctrl_lc_escalation.2339943332	May 05 02:01:02 PM PDT 24	May 05 02:01:08 PM PDT 24	1104537490 ps
T253	/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1374767649	May 05 01:58:25 PM PDT 24	May 05 02:03:25 PM PDT 24	4391034990 ps
T254	/workspace/coverage/default/8.sram_ctrl_stress_pipeline.728424943	May 05 01:58:59 PM PDT 24	May 05 02:03:12 PM PDT 24	40068559991 ps
T50	/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3411566873	May 05 01:59:29 PM PDT 24	May 05 02:00:06 PM PDT 24	5238847303 ps
T255	/workspace/coverage/default/31.sram_ctrl_max_throughput.2544446307	May 05 02:02:40 PM PDT 24	May 05 02:02:57 PM PDT 24	301380299 ps
T256	/workspace/coverage/default/15.sram_ctrl_executable.1547691434	May 05 01:59:46 PM PDT 24	May 05 02:15:08 PM PDT 24	10372217129 ps
T257	/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1297447149	May 05 01:59:37 PM PDT 24	May 05 01:59:48 PM PDT 24	244188144 ps
T258	/workspace/coverage/default/49.sram_ctrl_alert_test.2878270915	May 05 02:07:03 PM PDT 24	May 05 02:07:04 PM PDT 24	11408692 ps
T259	/workspace/coverage/default/6.sram_ctrl_mem_walk.1860150520	May 05 01:58:54 PM PDT 24	May 05 01:59:04 PM PDT 24	447770862 ps
T260	/workspace/coverage/default/19.sram_ctrl_mem_partial_access.247340000	May 05 02:00:21 PM PDT 24	May 05 02:00:27 PM PDT 24	156487831 ps
T261	/workspace/coverage/default/17.sram_ctrl_mem_walk.464677296	May 05 02:00:00 PM PDT 24	May 05 02:00:05 PM PDT 24	298980183 ps
T262	/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.326939007	May 05 02:06:03 PM PDT 24	May 05 02:07:45 PM PDT 24	148057133 ps
T263	/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.426824367	May 05 02:06:29 PM PDT 24	May 05 02:10:10 PM PDT 24	9297625174 ps
T264	/workspace/coverage/default/43.sram_ctrl_regwen.2928562238	May 05 02:05:34 PM PDT 24	May 05 02:16:34 PM PDT 24	10556820032 ps
T28	/workspace/coverage/default/0.sram_ctrl_lc_escalation.2303061100	May 05 01:58:22 PM PDT 24	May 05 01:58:29 PM PDT 24	1170499733 ps
T265	/workspace/coverage/default/41.sram_ctrl_bijection.3810018294	May 05 02:04:59 PM PDT 24	May 05 02:05:37 PM PDT 24	3955832271 ps
T266	/workspace/coverage/default/4.sram_ctrl_smoke.3192953152	May 05 01:58:42 PM PDT 24	May 05 01:59:16 PM PDT 24	470500638 ps
T267	/workspace/coverage/default/12.sram_ctrl_stress_pipeline.1909539136	May 05 01:59:24 PM PDT 24	May 05 02:03:16 PM PDT 24	10372606684 ps
T268	/workspace/coverage/default/49.sram_ctrl_lc_escalation.2014773816	May 05 02:06:52 PM PDT 24	May 05 02:06:56 PM PDT 24	613774417 ps
T269	/workspace/coverage/default/39.sram_ctrl_mem_partial_access.518092926	May 05 02:04:40 PM PDT 24	May 05 02:04:44 PM PDT 24	167713398 ps
T270	/workspace/coverage/default/17.sram_ctrl_access_during_key_req.1456329634	May 05 02:00:01 PM PDT 24	May 05 02:09:18 PM PDT 24	2636409892 ps
T271	/workspace/coverage/default/36.sram_ctrl_mem_walk.2625700882	May 05 02:03:56 PM PDT 24	May 05 02:04:06 PM PDT 24	711331359 ps
T272	/workspace/coverage/default/13.sram_ctrl_mem_walk.3033592126	May 05 01:59:33 PM PDT 24	May 05 01:59:42 PM PDT 24	3118612435 ps
T273	/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1363985507	May 05 01:59:10 PM PDT 24	May 05 02:08:28 PM PDT 24	27523346413 ps
T274	/workspace/coverage/default/5.sram_ctrl_lc_escalation.2840786627	May 05 01:58:47 PM PDT 24	May 05 01:58:49 PM PDT 24	508593141 ps
T275	/workspace/coverage/default/47.sram_ctrl_partial_access.465389277	May 05 02:06:20 PM PDT 24	May 05 02:06:33 PM PDT 24	746517743 ps
T276	/workspace/coverage/default/5.sram_ctrl_mem_partial_access.4289856073	May 05 01:58:49 PM PDT 24	May 05 01:58:52 PM PDT 24	574369048 ps
T277	/workspace/coverage/default/7.sram_ctrl_stress_all.3966665804	May 05 01:59:01 PM PDT 24	May 05 02:21:18 PM PDT 24	18802911194 ps
T278	/workspace/coverage/default/22.sram_ctrl_executable.3352400631	May 05 02:00:53 PM PDT 24	May 05 02:15:15 PM PDT 24	14054097263 ps
T279	/workspace/coverage/default/35.sram_ctrl_stress_all.3634338750	May 05 02:03:47 PM PDT 24	May 05 03:12:08 PM PDT 24	354696259344 ps
T280	/workspace/coverage/default/47.sram_ctrl_mem_walk.3749408674	May 05 02:06:39 PM PDT 24	May 05 02:06:48 PM PDT 24	472258858 ps
T281	/workspace/coverage/default/28.sram_ctrl_partial_access.2872776375	May 05 02:01:57 PM PDT 24	May 05 02:02:08 PM PDT 24	585239977 ps
T282	/workspace/coverage/default/11.sram_ctrl_stress_all.3181745681	May 05 01:59:23 PM PDT 24	May 05 02:15:35 PM PDT 24	43789208018 ps
T283	/workspace/coverage/default/47.sram_ctrl_executable.971997466	May 05 02:06:33 PM PDT 24	May 05 02:12:04 PM PDT 24	7546982313 ps
T284	/workspace/coverage/default/38.sram_ctrl_multiple_keys.2196325541	May 05 02:04:15 PM PDT 24	May 05 02:23:55 PM PDT 24	30120812616 ps
T285	/workspace/coverage/default/0.sram_ctrl_multiple_keys.1934815878	May 05 01:58:23 PM PDT 24	May 05 02:09:12 PM PDT 24	23660780330 ps
T286	/workspace/coverage/default/20.sram_ctrl_smoke.900333429	May 05 02:00:24 PM PDT 24	May 05 02:00:28 PM PDT 24	127026683 ps
T287	/workspace/coverage/default/32.sram_ctrl_executable.3170548034	May 05 02:02:59 PM PDT 24	May 05 02:26:46 PM PDT 24	73814002153 ps
T288	/workspace/coverage/default/25.sram_ctrl_stress_pipeline.528436594	May 05 02:01:23 PM PDT 24	May 05 02:04:30 PM PDT 24	7940187044 ps
T29	/workspace/coverage/default/45.sram_ctrl_lc_escalation.4101320540	May 05 02:06:02 PM PDT 24	May 05 02:06:07 PM PDT 24	3470193274 ps
T289	/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.411607438	May 05 02:06:11 PM PDT 24	May 05 02:06:57 PM PDT 24	217706368 ps
T290	/workspace/coverage/default/19.sram_ctrl_max_throughput.3272353427	May 05 02:00:19 PM PDT 24	May 05 02:00:26 PM PDT 24	61287852 ps
T291	/workspace/coverage/default/35.sram_ctrl_alert_test.4144830579	May 05 02:03:47 PM PDT 24	May 05 02:03:48 PM PDT 24	13462265 ps
T292	/workspace/coverage/default/5.sram_ctrl_multiple_keys.404350771	May 05 01:58:45 PM PDT 24	May 05 02:09:39 PM PDT 24	37931972183 ps
T293	/workspace/coverage/default/46.sram_ctrl_mem_walk.929449033	May 05 02:06:16 PM PDT 24	May 05 02:06:26 PM PDT 24	587365080 ps
T51	/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1232072476	May 05 02:02:22 PM PDT 24	May 05 02:02:50 PM PDT 24	527084618 ps
T294	/workspace/coverage/default/29.sram_ctrl_stress_pipeline.1266246687	May 05 02:02:11 PM PDT 24	May 05 02:07:41 PM PDT 24	8205291899 ps
T295	/workspace/coverage/default/14.sram_ctrl_smoke.768229365	May 05 01:59:33 PM PDT 24	May 05 02:00:29 PM PDT 24	1011360832 ps
T296	/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.306150496	May 05 02:01:07 PM PDT 24	May 05 02:01:37 PM PDT 24	2062199234 ps
T297	/workspace/coverage/default/32.sram_ctrl_mem_partial_access.2264623329	May 05 02:03:03 PM PDT 24	May 05 02:03:07 PM PDT 24	66027031 ps
T298	/workspace/coverage/default/10.sram_ctrl_mem_walk.3099456794	May 05 01:59:13 PM PDT 24	May 05 01:59:25 PM PDT 24	10846013999 ps
T299	/workspace/coverage/default/1.sram_ctrl_smoke.884864832	May 05 01:58:23 PM PDT 24	May 05 01:58:31 PM PDT 24	858552146 ps
T300	/workspace/coverage/default/25.sram_ctrl_mem_partial_access.2937322848	May 05 02:01:32 PM PDT 24	May 05 02:01:37 PM PDT 24	597512928 ps
T301	/workspace/coverage/default/48.sram_ctrl_ram_cfg.2537946264	May 05 02:06:46 PM PDT 24	May 05 02:06:47 PM PDT 24	66625136 ps
T302	/workspace/coverage/default/24.sram_ctrl_access_during_key_req.2645328999	May 05 02:01:12 PM PDT 24	May 05 02:11:59 PM PDT 24	2921839368 ps
T303	/workspace/coverage/default/26.sram_ctrl_mem_partial_access.3501079411	May 05 02:01:41 PM PDT 24	May 05 02:01:44 PM PDT 24	334133790 ps
T304	/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2439161254	May 05 02:05:15 PM PDT 24	May 05 02:10:50 PM PDT 24	113075489417 ps
T305	/workspace/coverage/default/3.sram_ctrl_access_during_key_req.166119428	May 05 01:58:39 PM PDT 24	May 05 02:11:17 PM PDT 24	3199497202 ps
T306	/workspace/coverage/default/13.sram_ctrl_regwen.1736604402	May 05 01:59:32 PM PDT 24	May 05 02:10:16 PM PDT 24	55136896751 ps
T307	/workspace/coverage/default/1.sram_ctrl_bijection.2914529850	May 05 01:58:26 PM PDT 24	May 05 01:59:43 PM PDT 24	60427064508 ps
T308	/workspace/coverage/default/12.sram_ctrl_max_throughput.2604600578	May 05 01:59:24 PM PDT 24	May 05 01:59:25 PM PDT 24	36712119 ps