Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	46007997	1			T1	3071		T2	417		T3	25569
triple_byte_access	2518687	1			T2	370		T3	22901		T4	3910
halfword_access	3783220	1			T2	502		T3	34456		T4	5874
byte_access	5052194	1			T2	765		T3	46050		T4	7682
zero_access	1270242	1			T2	157		T3	11530		T4	1928

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29255234

1

T1

1024

T2

1088

T3

70309

auto[1]

29377106

1

T1

2047

T2

1123

T3

70197

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22948725	1			T1	1024		T2	193		T3	12685
auto[0]	triple_byte_access	1255538	1			T2	183		T3	11529		T4	1979
auto[0]	halfword_access	1887703	1			T2	253		T3	17228		T4	2908
auto[0]	byte_access	2524184	1			T2	373		T3	23092		T4	3842
auto[0]	zero_access	639084	1			T2	86		T3	5775		T4	988
auto[1]	word_access	23059272	1			T1	2047		T2	224		T3	12884
auto[1]	triple_byte_access	1263149	1			T2	187		T3	11372		T4	1931
auto[1]	halfword_access	1895517	1			T2	249		T3	17228		T4	2966
auto[1]	byte_access	2528010	1			T2	392		T3	22958		T4	3840
auto[1]	zero_access	631158	1			T2	71		T3	5755		T4	940