Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13456955	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

54547792

1

T1

6671

T2

30599

T3

7666

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	33879238	1			T1	3255		T2	16808		T3	4667
values[0x0]	15714193	1			T1	1688		T2	8097		T3	2164
values[0x1]	18411316	1			T1	1728		T2	8729		T3	2583

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6705221	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

61299526

1

T1

6671

T2

32111

T3

8553

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	270169	1			T3	38		T8	877		T10	739
valid_sources[0x01]	274325	1			T3	45		T8	757		T10	859
valid_sources[0x02]	236202	1			T3	39		T8	887		T10	1040
valid_sources[0x03]	268620	1			T3	45		T8	837		T10	526
valid_sources[0x04]	255423	1			T3	47		T8	752		T10	695
valid_sources[0x05]	242458	1			T3	36		T8	794		T10	753
valid_sources[0x06]	288398	1			T3	42		T8	850		T10	813
valid_sources[0x07]	262856	1			T3	50		T4	14935		T8	707
valid_sources[0x08]	248975	1			T3	34		T8	917		T10	841
valid_sources[0x09]	232724	1			T3	38		T8	737		T10	597
valid_sources[0x0a]	261525	1			T3	41		T8	825		T10	918
valid_sources[0x0b]	230487	1			T3	41		T8	729		T10	1024
valid_sources[0x0c]	335318	1			T3	43		T8	829		T10	689
valid_sources[0x0d]	228844	1			T3	44		T8	763		T10	910
valid_sources[0x0e]	235303	1			T3	50		T8	919		T10	669
valid_sources[0x0f]	262262	1			T3	34		T8	807		T10	906
valid_sources[0x10]	250906	1			T3	41		T8	853		T10	672
valid_sources[0x11]	260068	1			T3	28		T8	858		T10	646
valid_sources[0x12]	305469	1			T3	20		T8	788		T10	895
valid_sources[0x13]	282145	1			T3	39		T8	830		T10	803
valid_sources[0x14]	309491	1			T3	53		T8	879		T10	818
valid_sources[0x15]	265993	1			T3	43		T8	836		T10	784
valid_sources[0x16]	257296	1			T3	39		T8	879		T10	927
valid_sources[0x17]	252879	1			T3	38		T8	1026		T10	1102
valid_sources[0x18]	229896	1			T3	38		T8	850		T10	465
valid_sources[0x19]	231593	1			T3	33		T8	847		T10	807
valid_sources[0x1a]	250687	1			T3	20		T8	877		T10	784
valid_sources[0x1b]	276961	1			T3	40		T8	915		T10	961
valid_sources[0x1c]	286577	1			T3	33		T8	803		T10	749
valid_sources[0x1d]	317297	1			T3	37		T8	932		T10	890
valid_sources[0x1e]	240328	1			T3	33		T8	831		T10	837
valid_sources[0x1f]	265934	1			T3	33		T8	863		T10	674
valid_sources[0x20]	278973	1			T3	36		T8	849		T10	795
valid_sources[0x21]	226427	1			T3	44		T8	951		T10	846
valid_sources[0x22]	248438	1			T3	32		T8	808		T10	800
valid_sources[0x23]	238312	1			T3	29		T8	819		T10	681
valid_sources[0x24]	283595	1			T3	36		T8	809		T10	617
valid_sources[0x25]	302661	1			T3	36		T8	751		T10	788
valid_sources[0x26]	289411	1			T3	27		T8	803		T10	977
valid_sources[0x27]	248265	1			T3	39		T8	820		T10	838
valid_sources[0x28]	241037	1			T3	24		T8	836		T10	752
valid_sources[0x29]	229061	1			T3	30		T8	856		T10	735
valid_sources[0x2a]	314933	1			T3	39		T8	704		T10	719
valid_sources[0x2b]	294705	1			T3	42		T8	751		T10	857
valid_sources[0x2c]	248268	1			T3	35		T8	810		T10	1033
valid_sources[0x2d]	237044	1			T3	37		T8	802		T10	702
valid_sources[0x2e]	294214	1			T3	38		T8	923		T10	675
valid_sources[0x2f]	245964	1			T3	34		T8	696		T10	745
valid_sources[0x30]	251089	1			T3	27		T8	846		T10	847
valid_sources[0x31]	268113	1			T3	37		T8	806		T10	918
valid_sources[0x32]	256031	1			T3	38		T8	844		T10	748
valid_sources[0x33]	284060	1			T3	26		T8	826		T9	3426
valid_sources[0x34]	284165	1			T3	35		T8	784		T10	768
valid_sources[0x35]	254709	1			T3	51		T8	875		T10	662
valid_sources[0x36]	273336	1			T3	28		T8	675		T10	900
valid_sources[0x37]	249019	1			T3	32		T8	945		T10	807
valid_sources[0x38]	302171	1			T3	35		T8	859		T10	1185
valid_sources[0x39]	254018	1			T3	48		T8	789		T10	1011
valid_sources[0x3a]	263440	1			T3	35		T8	871		T10	613
valid_sources[0x3b]	224917	1			T3	27		T8	766		T10	679
valid_sources[0x3c]	229276	1			T3	41		T8	792		T10	993
valid_sources[0x3d]	254817	1			T3	39		T8	863		T10	895
valid_sources[0x3e]	233521	1			T3	36		T8	903		T10	1182
valid_sources[0x3f]	229050	1			T3	38		T8	780		T10	735
valid_sources[0x40]	240116	1			T1	3335		T3	32		T8	796
valid_sources[0x41]	325747	1			T2	4026		T3	42		T8	911
valid_sources[0x42]	331751	1			T3	28		T8	850		T10	671
valid_sources[0x43]	252137	1			T3	41		T8	785		T10	768
valid_sources[0x44]	299526	1			T3	39		T8	723		T10	1014
valid_sources[0x45]	228858	1			T3	37		T8	922		T9	3426
valid_sources[0x46]	274143	1			T3	43		T8	847		T10	898
valid_sources[0x47]	239969	1			T3	35		T8	729		T10	725
valid_sources[0x48]	251884	1			T3	46		T8	897		T10	708
valid_sources[0x49]	245905	1			T3	39		T8	752		T10	675
valid_sources[0x4a]	256302	1			T3	41		T8	783		T10	830
valid_sources[0x4b]	254043	1			T3	38		T8	810		T10	886
valid_sources[0x4c]	269327	1			T3	35		T8	942		T10	654
valid_sources[0x4d]	336137	1			T3	35		T8	768		T10	679
valid_sources[0x4e]	311877	1			T3	39		T8	797		T10	662
valid_sources[0x4f]	247420	1			T3	31		T8	735		T10	703
valid_sources[0x50]	317121	1			T3	27		T8	842		T10	588
valid_sources[0x51]	296853	1			T3	40		T8	880		T10	729
valid_sources[0x52]	274826	1			T3	52		T8	812		T10	691
valid_sources[0x53]	293372	1			T3	42		T8	890		T10	909
valid_sources[0x54]	264831	1			T3	32		T8	829		T10	883
valid_sources[0x55]	276063	1			T3	41		T8	843		T10	686
valid_sources[0x56]	248536	1			T3	32		T8	776		T10	776
valid_sources[0x57]	280932	1			T3	32		T8	738		T10	665
valid_sources[0x58]	261243	1			T3	34		T8	885		T10	541
valid_sources[0x59]	254592	1			T3	31		T8	929		T10	900
valid_sources[0x5a]	330689	1			T3	29		T8	729		T10	966
valid_sources[0x5b]	232368	1			T3	39		T8	733		T10	567
valid_sources[0x5c]	326492	1			T3	39		T8	649		T10	762
valid_sources[0x5d]	262369	1			T3	32		T8	842		T10	941
valid_sources[0x5e]	246384	1			T3	48		T8	672		T10	680
valid_sources[0x5f]	227288	1			T3	40		T8	847		T10	795
valid_sources[0x60]	269617	1			T3	44		T8	660		T10	781
valid_sources[0x61]	231207	1			T3	52		T8	783		T10	660
valid_sources[0x62]	235184	1			T3	38		T8	776		T10	656
valid_sources[0x63]	235072	1			T3	36		T8	824		T10	623
valid_sources[0x64]	290860	1			T3	49		T8	702		T10	848
valid_sources[0x65]	273250	1			T2	684		T3	37		T8	743
valid_sources[0x66]	250408	1			T3	42		T8	723		T10	794
valid_sources[0x67]	256398	1			T3	35		T8	778		T10	643
valid_sources[0x68]	273868	1			T3	30		T8	541		T10	981
valid_sources[0x69]	257262	1			T3	35		T8	704		T10	718
valid_sources[0x6a]	222788	1			T3	31		T8	808		T10	756
valid_sources[0x6b]	346067	1			T3	36		T8	793		T10	965
valid_sources[0x6c]	271745	1			T3	41		T8	963		T10	1016
valid_sources[0x6d]	270792	1			T3	36		T8	842		T10	788
valid_sources[0x6e]	230299	1			T3	45		T8	849		T10	610
valid_sources[0x6f]	234003	1			T3	30		T8	876		T10	721
valid_sources[0x70]	259706	1			T3	27		T8	848		T10	913
valid_sources[0x71]	245188	1			T3	29		T8	803		T10	1062
valid_sources[0x72]	257133	1			T3	41		T8	784		T10	769
valid_sources[0x73]	346476	1			T3	44		T8	855		T10	663
valid_sources[0x74]	269058	1			T3	27		T8	863		T10	765
valid_sources[0x75]	266497	1			T3	36		T8	862		T10	730
valid_sources[0x76]	292293	1			T3	41		T8	793		T10	1055
valid_sources[0x77]	228790	1			T3	52		T8	720		T10	743
valid_sources[0x78]	240060	1			T3	37		T8	863		T10	799
valid_sources[0x79]	248378	1			T3	35		T8	784		T10	731
valid_sources[0x7a]	250046	1			T3	33		T8	771		T10	894
valid_sources[0x7b]	244916	1			T3	26		T8	835		T10	811
valid_sources[0x7c]	229704	1			T3	35		T8	816		T10	742
valid_sources[0x7d]	261644	1			T3	33		T8	815		T10	940
valid_sources[0x7e]	329736	1			T3	31		T8	662		T10	738
valid_sources[0x7f]	244340	1			T3	32		T8	808		T10	911
valid_sources[0x80]	268806	1			T3	27		T8	748		T10	658

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27156072

1

T1

3255

T2

15291

T3

3790

values[0x0]

all_enables

biggest_size

13693921

1

T1

1688

T2

7661

T3

1905

values[0x1]

all_enables

biggest_size

13697799

1

T1

1728

T2

7647

T3

1971

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33236	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

147144

1

T4

2

T8

2

T9

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	52290	1			T17	14		T5	38		T18	743
values[0x0]	61644	1			T1	2		T2	4		T3	1
values[0x1]	66446	1			T3	1		T4	5		T8	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25038	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

155342

1

T4

3

T8

2

T9

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	731	1			T17	2		T18	44		T47	1
valid_sources[0x01]	494	1			T47	1		T33	18		T31	1
valid_sources[0x02]	504	1			T18	12		T7	15		T33	21
valid_sources[0x03]	490	1			T48	1		T29	1		T33	14
valid_sources[0x04]	631	1			T18	53		T83	1		T33	6
valid_sources[0x05]	759	1			T10	5		T17	1		T18	49
valid_sources[0x06]	647	1			T18	1		T82	2		T33	13
valid_sources[0x07]	742	1			T18	35		T29	1		T33	11
valid_sources[0x08]	651	1			T18	1		T33	16		T62	2
valid_sources[0x09]	787	1			T28	1		T18	18		T47	1
valid_sources[0x0a]	626	1			T18	9		T6	20		T33	8
valid_sources[0x0b]	785	1			T18	12		T47	1		T33	13
valid_sources[0x0c]	531	1			T18	2		T33	9		T63	1
valid_sources[0x0d]	641	1			T48	2		T101	6		T33	16
valid_sources[0x0e]	800	1			T18	3		T33	11		T34	7
valid_sources[0x0f]	567	1			T18	10		T33	8		T63	2
valid_sources[0x10]	811	1			T1	2		T18	1		T6	11
valid_sources[0x11]	581	1			T33	11		T63	1		T50	8
valid_sources[0x12]	992	1			T18	17		T29	3		T33	13
valid_sources[0x13]	604	1			T18	18		T14	1		T84	1
valid_sources[0x14]	541	1			T18	18		T33	6		T141	8
valid_sources[0x15]	591	1			T17	3		T18	23		T33	16
valid_sources[0x16]	617	1			T18	4		T29	2		T33	20
valid_sources[0x17]	1021	1			T17	4		T18	19		T33	13
valid_sources[0x18]	613	1			T18	12		T99	2		T29	1
valid_sources[0x19]	626	1			T18	14		T135	7		T33	15
valid_sources[0x1a]	901	1			T18	11		T33	9		T24	1
valid_sources[0x1b]	733	1			T47	1		T33	12		T34	1
valid_sources[0x1c]	867	1			T28	1		T18	8		T47	1
valid_sources[0x1d]	864	1			T18	25		T145	1		T33	8
valid_sources[0x1e]	737	1			T17	3		T18	18		T33	8
valid_sources[0x1f]	681	1			T18	1		T7	6		T29	1
valid_sources[0x20]	1179	1			T18	29		T33	7		T146	1
valid_sources[0x21]	606	1			T18	36		T33	16		T34	33
valid_sources[0x22]	619	1			T18	12		T29	2		T33	15
valid_sources[0x23]	1153	1			T2	1		T18	12		T33	13
valid_sources[0x24]	910	1			T11	4		T29	1		T33	10
valid_sources[0x25]	1149	1			T18	1		T33	16		T34	1
valid_sources[0x26]	779	1			T4	1		T18	14		T7	3
valid_sources[0x27]	547	1			T18	27		T33	15		T62	1
valid_sources[0x28]	532	1			T18	23		T33	15		T62	1
valid_sources[0x29]	671	1			T17	5		T18	5		T76	1
valid_sources[0x2a]	562	1			T18	33		T29	1		T33	11
valid_sources[0x2b]	564	1			T33	19		T45	1		T50	3
valid_sources[0x2c]	637	1			T18	1		T33	17		T31	1
valid_sources[0x2d]	528	1			T18	5		T139	7		T33	16
valid_sources[0x2e]	506	1			T18	16		T47	1		T33	9
valid_sources[0x2f]	798	1			T18	17		T47	2		T33	8
valid_sources[0x30]	986	1			T18	5		T33	15		T146	1
valid_sources[0x31]	1019	1			T18	11		T147	1		T29	1
valid_sources[0x32]	699	1			T18	23		T135	1		T33	20
valid_sources[0x33]	749	1			T135	2		T33	12		T34	18
valid_sources[0x34]	926	1			T33	16		T31	1		T34	13
valid_sources[0x35]	823	1			T18	8		T33	17		T63	1
valid_sources[0x36]	470	1			T29	2		T33	11		T63	1
valid_sources[0x37]	582	1			T18	27		T148	1		T29	1
valid_sources[0x38]	874	1			T18	2		T47	1		T33	14
valid_sources[0x39]	587	1			T18	11		T33	10		T31	1
valid_sources[0x3a]	554	1			T8	5		T17	4		T18	26
valid_sources[0x3b]	518	1			T18	5		T33	13		T31	1
valid_sources[0x3c]	550	1			T18	32		T29	1		T33	12
valid_sources[0x3d]	485	1			T18	28		T33	13		T24	1
valid_sources[0x3e]	667	1			T17	1		T33	15		T31	1
valid_sources[0x3f]	438	1			T18	24		T33	6		T25	1
valid_sources[0x40]	461	1			T17	4		T18	1		T33	12
valid_sources[0x41]	542	1			T18	13		T33	8		T50	8
valid_sources[0x42]	642	1			T18	22		T6	39		T29	1
valid_sources[0x43]	767	1			T18	12		T33	14		T63	1
valid_sources[0x44]	730	1			T17	3		T18	4		T29	1
valid_sources[0x45]	470	1			T18	18		T7	1		T82	1
valid_sources[0x46]	756	1			T18	2		T33	11		T31	1
valid_sources[0x47]	809	1			T17	1		T18	2		T29	3
valid_sources[0x48]	555	1			T6	1		T29	1		T33	14
valid_sources[0x49]	718	1			T18	1		T33	11		T63	1
valid_sources[0x4a]	673	1			T18	31		T6	7		T29	2
valid_sources[0x4b]	563	1			T64	2		T18	2		T139	5
valid_sources[0x4c]	441	1			T99	1		T33	11		T63	1
valid_sources[0x4d]	769	1			T18	4		T47	1		T30	65
valid_sources[0x4e]	451	1			T13	2		T18	8		T29	1
valid_sources[0x4f]	636	1			T17	3		T18	1		T7	10
valid_sources[0x50]	545	1			T18	4		T147	1		T33	10
valid_sources[0x51]	585	1			T18	15		T33	9		T62	1
valid_sources[0x52]	1273	1			T28	1		T32	1		T18	18
valid_sources[0x53]	682	1			T33	19		T31	1		T34	7
valid_sources[0x54]	617	1			T3	1		T18	7		T33	18
valid_sources[0x55]	649	1			T33	12		T39	2		T34	13
valid_sources[0x56]	553	1			T18	2		T33	15		T50	7
valid_sources[0x57]	664	1			T149	1		T29	2		T33	13
valid_sources[0x58]	790	1			T18	14		T6	32		T7	6
valid_sources[0x59]	640	1			T18	4		T82	1		T29	4
valid_sources[0x5a]	580	1			T18	11		T29	1		T33	16
valid_sources[0x5b]	696	1			T18	54		T33	5		T63	1
valid_sources[0x5c]	571	1			T18	3		T33	8		T63	1
valid_sources[0x5d]	457	1			T17	2		T18	10		T47	1
valid_sources[0x5e]	636	1			T17	1		T18	12		T33	9
valid_sources[0x5f]	697	1			T18	1		T33	9		T34	1
valid_sources[0x60]	626	1			T18	12		T82	2		T33	13
valid_sources[0x61]	735	1			T18	32		T47	1		T33	12
valid_sources[0x62]	1217	1			T18	8		T47	1		T29	1
valid_sources[0x63]	467	1			T18	2		T33	11		T31	1
valid_sources[0x64]	619	1			T18	13		T33	20		T25	1
valid_sources[0x65]	799	1			T18	25		T47	1		T33	11
valid_sources[0x66]	613	1			T18	50		T147	1		T29	1
valid_sources[0x67]	542	1			T18	21		T60	1		T33	16
valid_sources[0x68]	661	1			T5	7		T18	17		T6	3
valid_sources[0x69]	524	1			T18	11		T33	18		T34	1
valid_sources[0x6a]	663	1			T18	11		T29	1		T33	9
valid_sources[0x6b]	868	1			T5	7		T18	8		T15	1
valid_sources[0x6c]	620	1			T17	1		T26	1		T29	1
valid_sources[0x6d]	549	1			T18	3		T6	33		T99	1
valid_sources[0x6e]	566	1			T5	12		T18	21		T47	1
valid_sources[0x6f]	625	1			T17	3		T18	1		T29	1
valid_sources[0x70]	767	1			T18	23		T48	1		T135	2
valid_sources[0x71]	1034	1			T18	9		T29	1		T33	9
valid_sources[0x72]	532	1			T18	18		T33	9		T150	1
valid_sources[0x73]	624	1			T18	2		T33	12		T63	2
valid_sources[0x74]	649	1			T18	14		T33	9		T50	5
valid_sources[0x75]	444	1			T18	23		T35	1		T29	1
valid_sources[0x76]	593	1			T33	15		T62	1		T31	1
valid_sources[0x77]	828	1			T82	2		T29	1		T33	10
valid_sources[0x78]	735	1			T5	6		T18	16		T33	12
valid_sources[0x79]	545	1			T17	6		T18	1		T33	9
valid_sources[0x7a]	824	1			T18	16		T33	12		T31	2
valid_sources[0x7b]	482	1			T18	10		T82	1		T33	9
valid_sources[0x7c]	778	1			T17	1		T18	1		T6	4
valid_sources[0x7d]	628	1			T33	12		T151	1		T34	11
valid_sources[0x7e]	749	1			T18	16		T33	14		T152	2
valid_sources[0x7f]	944	1			T33	15		T62	1		T31	1
valid_sources[0x80]	1020	1			T18	6		T33	21		T63	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

40134

1

T17

6

T5

16

T18

665

values[0x0]

all_enables

biggest_size

54143

1

T4

2

T8

1

T9

1

values[0x1]

all_enables

biggest_size

52867

1

T8

1

T17

9

T5

2