Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13254422

1

T2

3035

T3

1748

T4

2836

full_word

50444387

1

T1

6671

T2

30599

T3

7666

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	63698499	1			T1	6671		T2	33634		T3	9414
auto[TlIntgErrCmd]	105	1			T106	2		T107	5		T108	4
auto[TlIntgErrData]	102	1			T106	4		T107	4		T108	7
auto[TlIntgErrBoth]	103	1			T106	4		T107	1		T108	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29474973

1

T1

3255

T2

16808

T3

4667

auto[1]

34223836

1

T1

3416

T2

16826

T3

4747

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrData]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6360741	1			T2	1517		T3	877		T4	1026
auto[TlIntgErrNone]	partial	auto[1]	6893387	1			T2	1518		T3	871		T4	1810
auto[TlIntgErrNone]	full_word	auto[0]	23114100	1			T1	3255		T2	15291		T3	3790
auto[TlIntgErrNone]	full_word	auto[1]	27330271	1			T1	3416		T2	15308		T3	3876
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T107	1		T120	2		T121	1
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T106	2		T107	4		T108	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T122	1		T123	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T124	1		T125	1		-	-
auto[TlIntgErrData]	partial	auto[0]	52	1			T106	2		T107	3		T108	4
auto[TlIntgErrData]	partial	auto[1]	48	1			T106	2		T107	1		T108	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T108	1		T126	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T106	1		T108	4		T120	2
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T106	3		T107	1		T108	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T127	1		T128	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T108	1		T120	1		T121	1