Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	752467	1			T8	13052		T14	91		T15	4
auto[1]	10325341	1			T1	3255		T2	7665		T3	4666
auto[2]	619257	1			T8	12887		T6	1		T14	76
auto[3]	10208346	1			T1	3415		T2	7646		T3	4746

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13680767	1			T1	6670		T2	12582		T3	6248
auto[1]	2155597	1			T2	1324		T3	1416		T4	16
auto[2]	2137566	1			T2	1290		T3	1453		T4	9
auto[3]	3931481	1			T2	115		T3	295		T4	1

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7921513

1

T1

6664

T2

15299

T3

9404

auto[1]

13983898

1

T1

6

T2

12

T3

8

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	296707	1			T139	10320		T29	2108		T33	543
auto[0]	auto[0]	auto[1]	30556	1			T14	1		T139	999		T83	3
auto[0]	auto[0]	auto[2]	30703	1			T139	985		T83	3		T29	207
auto[0]	auto[0]	auto[3]	10726	1			T14	88		T15	4		T139	94
auto[0]	auto[1]	auto[0]	2944198	1			T1	3252		T2	6304		T3	3090
auto[0]	auto[1]	auto[1]	320903	1			T2	663		T3	697		T4	10
auto[0]	auto[1]	auto[2]	297150	1			T2	629		T3	733		T4	2
auto[0]	auto[1]	auto[3]	77259	1			T2	62		T3	143		T9	102
auto[0]	auto[2]	auto[0]	256265	1			T6	1		T139	9344		T29	1965
auto[0]	auto[2]	auto[1]	26828	1			T14	12		T139	999		T83	26
auto[0]	auto[2]	auto[2]	24041	1			T139	682		T29	135		T33	41
auto[0]	auto[2]	auto[3]	8349	1			T14	64		T15	2		T139	62
auto[0]	auto[3]	auto[0]	2908374	1			T1	3412		T2	6270		T3	3155
auto[0]	auto[3]	auto[1]	294286	1			T2	658		T3	716		T4	6
auto[0]	auto[3]	auto[2]	316284	1			T2	660		T3	718		T4	7
auto[0]	auto[3]	auto[3]	78884	1			T2	53		T3	152		T4	1
auto[1]	auto[0]	auto[0]	12911	1			T8	430		T139	14		T29	2
auto[1]	auto[0]	auto[1]	56843	1			T8	1887		T139	1		T103	4829
auto[1]	auto[0]	auto[2]	56550	1			T8	1982		T103	4891		T140	3747
auto[1]	auto[0]	auto[3]	257471	1			T8	8753		T14	2		T83	1
auto[1]	auto[1]	auto[0]	3625304	1			T1	3		T2	4		T3	1
auto[1]	auto[1]	auto[1]	704175	1			T2	2		T3	1		T8	2237
auto[1]	auto[1]	auto[2]	675752	1			T2	1		T3	1		T8	1230
auto[1]	auto[1]	auto[3]	1680600	1			T8	9924		T10	52104		T17	1
auto[1]	auto[2]	auto[0]	11680	1			T8	233		T139	13		T141	5
auto[1]	auto[2]	auto[1]	51791	1			T8	1124		T139	1		T29	1
auto[1]	auto[2]	auto[2]	43860	1			T8	2100		T103	3202		T140	2586
auto[1]	auto[2]	auto[3]	196443	1			T8	9430		T103	14462		T140	11531
auto[1]	auto[3]	auto[0]	3625328	1			T1	3		T2	4		T3	2
auto[1]	auto[3]	auto[1]	670215	1			T2	1		T3	2		T8	479
auto[1]	auto[3]	auto[2]	693226	1			T3	1		T8	2423		T10	11655
auto[1]	auto[3]	auto[3]	1621749	1			T8	11115		T10	52508		T60	677