Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	304279320	143154	0	0
ctrl_regwen_rd_A	304279320	5651	0	0
exec_rd_A	304279320	4596	0	0
exec_regwen_rd_A	304279320	5504	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304279320	143154	0	0
T6	321101	0	0	0
T7	188330	0	0	0
T16	65727	0	0	0
T18	108798	3626	0	0
T33	0	3427	0	0
T34	0	985	0	0
T47	325498	0	0	0
T49	25347	0	0	0
T50	0	2264	0	0
T51	0	2138	0	0
T52	0	3193	0	0
T53	0	8037	0	0
T54	0	2244	0	0
T55	0	4017	0	0
T56	0	4746	0	0
T57	69440	0	0	0
T58	10320	0	0	0
T59	78943	0	0	0
T60	267936	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304279320	5651	0	0
T34	118201	180	0	0
T41	14830	0	0	0
T42	2918	0	0	0
T43	1990	0	0	0
T44	474223	0	0	0
T45	2125	0	0	0
T46	1894	0	0	0
T51	0	625	0	0
T54	0	658	0	0
T109	0	105	0	0
T110	0	310	0	0
T111	0	555	0	0
T112	0	260	0	0
T113	0	598	0	0
T114	0	505	0	0
T115	0	136	0	0
T116	4776	0	0	0
T117	7195	0	0	0
T118	22955	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304279320	4596	0	0
T34	118201	174	0	0
T41	14830	0	0	0
T42	2918	0	0	0
T43	1990	0	0	0
T44	474223	0	0	0
T45	2125	0	0	0
T46	1894	0	0	0
T51	0	414	0	0
T54	0	456	0	0
T109	0	44	0	0
T110	0	319	0	0
T111	0	470	0	0
T112	0	188	0	0
T113	0	538	0	0
T114	0	434	0	0
T115	0	63	0	0
T116	4776	0	0	0
T117	7195	0	0	0
T118	22955	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304279320	5504	0	0
T34	118201	158	0	0
T41	14830	0	0	0
T42	2918	0	0	0
T43	1990	0	0	0
T44	474223	0	0	0
T45	2125	0	0	0
T46	1894	0	0	0
T51	0	611	0	0
T54	0	659	0	0
T109	0	66	0	0
T110	0	381	0	0
T111	0	572	0	0
T112	0	252	0	0
T113	0	613	0	0
T114	0	373	0	0
T115	0	125	0	0
T116	4776	0	0	0
T117	7195	0	0	0
T118	22955	0	0	0