| T800 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3915010521 |
|
|
May 07 03:32:57 PM PDT 24 |
May 07 03:37:16 PM PDT 24 |
10394604027 ps |
| T38 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.1826154178 |
|
|
May 07 03:32:41 PM PDT 24 |
May 07 03:32:44 PM PDT 24 |
526341191 ps |
| T801 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1376939506 |
|
|
May 07 03:33:27 PM PDT 24 |
May 07 03:40:16 PM PDT 24 |
19373596644 ps |
| T802 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3228917590 |
|
|
May 07 03:34:25 PM PDT 24 |
May 07 03:34:57 PM PDT 24 |
112228126 ps |
| T803 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.1716499243 |
|
|
May 07 03:33:48 PM PDT 24 |
May 07 03:34:17 PM PDT 24 |
343509477 ps |
| T804 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.3152223977 |
|
|
May 07 03:35:58 PM PDT 24 |
May 07 03:36:01 PM PDT 24 |
138024003 ps |
| T805 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.4199896451 |
|
|
May 07 03:35:02 PM PDT 24 |
May 07 03:36:28 PM PDT 24 |
135650475 ps |
| T806 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.2937298439 |
|
|
May 07 03:33:10 PM PDT 24 |
May 07 03:39:34 PM PDT 24 |
13975150857 ps |
| T807 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.55729638 |
|
|
May 07 03:33:19 PM PDT 24 |
May 07 03:43:40 PM PDT 24 |
1813268886 ps |
| T808 |
/workspace/coverage/default/16.sram_ctrl_alert_test.3713707736 |
|
|
May 07 03:33:39 PM PDT 24 |
May 07 03:33:41 PM PDT 24 |
30892460 ps |
| T809 |
/workspace/coverage/default/30.sram_ctrl_partial_access.245092441 |
|
|
May 07 03:34:53 PM PDT 24 |
May 07 03:35:42 PM PDT 24 |
670932455 ps |
| T810 |
/workspace/coverage/default/10.sram_ctrl_executable.499420393 |
|
|
May 07 03:33:05 PM PDT 24 |
May 07 04:11:01 PM PDT 24 |
26198545309 ps |
| T811 |
/workspace/coverage/default/24.sram_ctrl_executable.2713094187 |
|
|
May 07 03:34:18 PM PDT 24 |
May 07 04:01:48 PM PDT 24 |
10707602799 ps |
| T812 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.61165207 |
|
|
May 07 03:33:33 PM PDT 24 |
May 07 03:40:16 PM PDT 24 |
37338458405 ps |
| T813 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.345553603 |
|
|
May 07 03:32:59 PM PDT 24 |
May 07 03:33:07 PM PDT 24 |
603322165 ps |
| T814 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.1617734101 |
|
|
May 07 03:32:47 PM PDT 24 |
May 07 03:32:56 PM PDT 24 |
541882117 ps |
| T815 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.3136890662 |
|
|
May 07 03:34:08 PM PDT 24 |
May 07 03:34:12 PM PDT 24 |
85094726 ps |
| T816 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3931653523 |
|
|
May 07 03:32:33 PM PDT 24 |
May 07 03:33:38 PM PDT 24 |
239769540 ps |
| T817 |
/workspace/coverage/default/30.sram_ctrl_bijection.2556685563 |
|
|
May 07 03:34:49 PM PDT 24 |
May 07 03:35:20 PM PDT 24 |
3538519450 ps |
| T818 |
/workspace/coverage/default/47.sram_ctrl_partial_access.2680739085 |
|
|
May 07 03:36:53 PM PDT 24 |
May 07 03:37:43 PM PDT 24 |
4706634413 ps |
| T819 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2144264343 |
|
|
May 07 03:37:09 PM PDT 24 |
May 07 03:37:42 PM PDT 24 |
97322645 ps |
| T820 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2798913451 |
|
|
May 07 03:32:34 PM PDT 24 |
May 07 03:35:16 PM PDT 24 |
2278201921 ps |
| T821 |
/workspace/coverage/default/17.sram_ctrl_alert_test.1730720230 |
|
|
May 07 03:33:39 PM PDT 24 |
May 07 03:33:40 PM PDT 24 |
11509130 ps |
| T822 |
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.3313601599 |
|
|
May 07 03:34:06 PM PDT 24 |
May 07 03:47:28 PM PDT 24 |
5231334166 ps |
| T823 |
/workspace/coverage/default/13.sram_ctrl_executable.1785645805 |
|
|
May 07 03:33:16 PM PDT 24 |
May 07 03:47:58 PM PDT 24 |
11020082479 ps |
| T824 |
/workspace/coverage/default/2.sram_ctrl_regwen.1686074904 |
|
|
May 07 03:32:39 PM PDT 24 |
May 07 03:42:44 PM PDT 24 |
7113066359 ps |
| T825 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.1401259917 |
|
|
May 07 03:34:08 PM PDT 24 |
May 07 03:50:17 PM PDT 24 |
41636877640 ps |
| T826 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.1697707802 |
|
|
May 07 03:35:29 PM PDT 24 |
May 07 03:35:50 PM PDT 24 |
92196642 ps |
| T827 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.4087484920 |
|
|
May 07 03:37:13 PM PDT 24 |
May 07 03:37:20 PM PDT 24 |
809878055 ps |
| T828 |
/workspace/coverage/default/3.sram_ctrl_partial_access.599814199 |
|
|
May 07 03:32:39 PM PDT 24 |
May 07 03:32:52 PM PDT 24 |
878103328 ps |
| T829 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2479855443 |
|
|
May 07 03:35:02 PM PDT 24 |
May 07 03:39:56 PM PDT 24 |
11829407514 ps |
| T830 |
/workspace/coverage/default/7.sram_ctrl_smoke.857769760 |
|
|
May 07 03:32:58 PM PDT 24 |
May 07 03:33:12 PM PDT 24 |
232214896 ps |
| T831 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.3901758900 |
|
|
May 07 03:33:01 PM PDT 24 |
May 07 03:35:49 PM PDT 24 |
2779305069 ps |
| T832 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.2638098326 |
|
|
May 07 03:34:49 PM PDT 24 |
May 07 03:38:06 PM PDT 24 |
19000804328 ps |
| T833 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.1760708043 |
|
|
May 07 03:33:40 PM PDT 24 |
May 07 03:36:12 PM PDT 24 |
138017699 ps |
| T834 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.1252483664 |
|
|
May 07 03:33:44 PM PDT 24 |
May 07 03:38:45 PM PDT 24 |
6515357258 ps |
| T835 |
/workspace/coverage/default/5.sram_ctrl_bijection.3007799286 |
|
|
May 07 03:32:49 PM PDT 24 |
May 07 03:33:31 PM PDT 24 |
2688628416 ps |
| T836 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1700666282 |
|
|
May 07 03:32:41 PM PDT 24 |
May 07 03:32:44 PM PDT 24 |
169937246 ps |
| T837 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.1170438877 |
|
|
May 07 03:35:06 PM PDT 24 |
May 07 03:35:08 PM PDT 24 |
33884761 ps |
| T838 |
/workspace/coverage/default/5.sram_ctrl_regwen.1422590076 |
|
|
May 07 03:32:50 PM PDT 24 |
May 07 03:43:12 PM PDT 24 |
20705361573 ps |
| T839 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.125248458 |
|
|
May 07 03:35:13 PM PDT 24 |
May 07 03:35:15 PM PDT 24 |
79296156 ps |
| T840 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.1741891297 |
|
|
May 07 03:33:12 PM PDT 24 |
May 07 03:33:16 PM PDT 24 |
187520210 ps |
| T841 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.3451055789 |
|
|
May 07 03:32:30 PM PDT 24 |
May 07 03:48:40 PM PDT 24 |
4341750664 ps |
| T842 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.1706053517 |
|
|
May 07 03:35:56 PM PDT 24 |
May 07 03:35:57 PM PDT 24 |
29482675 ps |
| T843 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.236430004 |
|
|
May 07 03:34:17 PM PDT 24 |
May 07 03:41:03 PM PDT 24 |
10798150175 ps |
| T844 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.1539661966 |
|
|
May 07 03:35:40 PM PDT 24 |
May 07 03:45:18 PM PDT 24 |
2328650480 ps |
| T845 |
/workspace/coverage/default/34.sram_ctrl_smoke.2385065743 |
|
|
May 07 03:35:17 PM PDT 24 |
May 07 03:36:55 PM PDT 24 |
650501557 ps |
| T846 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.278650356 |
|
|
May 07 03:33:10 PM PDT 24 |
May 07 03:33:35 PM PDT 24 |
1480819877 ps |
| T847 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2778282117 |
|
|
May 07 03:32:28 PM PDT 24 |
May 07 03:32:33 PM PDT 24 |
205426992 ps |
| T848 |
/workspace/coverage/default/23.sram_ctrl_regwen.1249857086 |
|
|
May 07 03:34:13 PM PDT 24 |
May 07 03:50:03 PM PDT 24 |
48839193274 ps |
| T849 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.585053765 |
|
|
May 07 03:33:54 PM PDT 24 |
May 07 03:36:29 PM PDT 24 |
6019263826 ps |
| T850 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.3681178128 |
|
|
May 07 03:34:58 PM PDT 24 |
May 07 03:38:44 PM PDT 24 |
4787011236 ps |
| T851 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.23046248 |
|
|
May 07 03:32:51 PM PDT 24 |
May 07 03:37:51 PM PDT 24 |
17384802668 ps |
| T852 |
/workspace/coverage/default/6.sram_ctrl_executable.850543723 |
|
|
May 07 03:32:57 PM PDT 24 |
May 07 03:51:18 PM PDT 24 |
3781661572 ps |
| T853 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3164064715 |
|
|
May 07 03:33:06 PM PDT 24 |
May 07 03:33:58 PM PDT 24 |
122003525 ps |
| T854 |
/workspace/coverage/default/44.sram_ctrl_bijection.3837498188 |
|
|
May 07 03:36:29 PM PDT 24 |
May 07 03:37:21 PM PDT 24 |
10990611141 ps |
| T855 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.1082252396 |
|
|
May 07 03:33:16 PM PDT 24 |
May 07 03:40:09 PM PDT 24 |
93156958129 ps |
| T856 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.283184414 |
|
|
May 07 03:33:01 PM PDT 24 |
May 07 03:34:13 PM PDT 24 |
962899717 ps |
| T857 |
/workspace/coverage/default/14.sram_ctrl_regwen.3676078381 |
|
|
May 07 03:33:28 PM PDT 24 |
May 07 03:45:28 PM PDT 24 |
2448202137 ps |
| T858 |
/workspace/coverage/default/31.sram_ctrl_regwen.2079147316 |
|
|
May 07 03:35:01 PM PDT 24 |
May 07 03:38:23 PM PDT 24 |
10446595893 ps |
| T859 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.2039352745 |
|
|
May 07 03:36:23 PM PDT 24 |
May 07 03:48:48 PM PDT 24 |
2997407810 ps |
| T860 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.591198405 |
|
|
May 07 03:35:56 PM PDT 24 |
May 07 03:36:39 PM PDT 24 |
389557879 ps |
| T861 |
/workspace/coverage/default/12.sram_ctrl_partial_access.2690287677 |
|
|
May 07 03:33:10 PM PDT 24 |
May 07 03:33:27 PM PDT 24 |
3738783461 ps |
| T862 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.3299671916 |
|
|
May 07 03:36:35 PM PDT 24 |
May 07 03:36:36 PM PDT 24 |
43333740 ps |
| T863 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.250636694 |
|
|
May 07 03:35:29 PM PDT 24 |
May 07 03:35:32 PM PDT 24 |
150946916 ps |
| T864 |
/workspace/coverage/default/18.sram_ctrl_partial_access.3705560293 |
|
|
May 07 03:33:45 PM PDT 24 |
May 07 03:34:13 PM PDT 24 |
209444209 ps |
| T865 |
/workspace/coverage/default/25.sram_ctrl_stress_all.3534301377 |
|
|
May 07 03:34:30 PM PDT 24 |
May 07 03:40:23 PM PDT 24 |
4261311346 ps |
| T113 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.4190414221 |
|
|
May 07 03:36:34 PM PDT 24 |
May 07 03:44:27 PM PDT 24 |
12341176065 ps |
| T866 |
/workspace/coverage/default/26.sram_ctrl_bijection.2352130970 |
|
|
May 07 03:34:25 PM PDT 24 |
May 07 03:34:42 PM PDT 24 |
1556702423 ps |
| T867 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.1552455384 |
|
|
May 07 03:33:00 PM PDT 24 |
May 07 03:33:07 PM PDT 24 |
813024234 ps |
| T868 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.948200922 |
|
|
May 07 03:37:01 PM PDT 24 |
May 07 03:38:27 PM PDT 24 |
473898372 ps |
| T869 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.246082202 |
|
|
May 07 03:34:05 PM PDT 24 |
May 07 03:40:55 PM PDT 24 |
3802652039 ps |
| T870 |
/workspace/coverage/default/41.sram_ctrl_executable.4205436601 |
|
|
May 07 03:36:14 PM PDT 24 |
May 07 03:49:56 PM PDT 24 |
2484591239 ps |
| T871 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.834400292 |
|
|
May 07 03:34:03 PM PDT 24 |
May 07 03:34:09 PM PDT 24 |
333851436 ps |
| T872 |
/workspace/coverage/default/17.sram_ctrl_bijection.2705963769 |
|
|
May 07 03:33:38 PM PDT 24 |
May 07 03:34:35 PM PDT 24 |
13242291469 ps |
| T873 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.610249480 |
|
|
May 07 03:37:08 PM PDT 24 |
May 07 03:41:24 PM PDT 24 |
10446927831 ps |
| T874 |
/workspace/coverage/default/37.sram_ctrl_partial_access.4218572962 |
|
|
May 07 03:35:34 PM PDT 24 |
May 07 03:35:36 PM PDT 24 |
167330517 ps |
| T875 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.498737223 |
|
|
May 07 03:33:14 PM PDT 24 |
May 07 03:50:42 PM PDT 24 |
2449210830 ps |
| T876 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3400490600 |
|
|
May 07 03:32:39 PM PDT 24 |
May 07 03:38:08 PM PDT 24 |
17834973465 ps |
| T114 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2388215156 |
|
|
May 07 03:35:20 PM PDT 24 |
May 07 03:36:28 PM PDT 24 |
6333162550 ps |
| T877 |
/workspace/coverage/default/18.sram_ctrl_bijection.1667466275 |
|
|
May 07 03:33:41 PM PDT 24 |
May 07 03:34:29 PM PDT 24 |
4621095734 ps |
| T878 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.985298448 |
|
|
May 07 03:34:40 PM PDT 24 |
May 07 03:54:31 PM PDT 24 |
17931922553 ps |
| T879 |
/workspace/coverage/default/10.sram_ctrl_partial_access.3347728445 |
|
|
May 07 03:33:05 PM PDT 24 |
May 07 03:33:21 PM PDT 24 |
963473090 ps |
| T880 |
/workspace/coverage/default/22.sram_ctrl_executable.3622844177 |
|
|
May 07 03:34:07 PM PDT 24 |
May 07 03:41:51 PM PDT 24 |
38686484561 ps |
| T881 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.89160591 |
|
|
May 07 03:32:46 PM PDT 24 |
May 07 03:33:28 PM PDT 24 |
100411675 ps |
| T882 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.657875029 |
|
|
May 07 03:33:05 PM PDT 24 |
May 07 03:33:14 PM PDT 24 |
2643972867 ps |
| T883 |
/workspace/coverage/default/15.sram_ctrl_alert_test.2376841485 |
|
|
May 07 03:33:28 PM PDT 24 |
May 07 03:33:29 PM PDT 24 |
36629856 ps |
| T884 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.3346350814 |
|
|
May 07 03:34:07 PM PDT 24 |
May 07 03:34:13 PM PDT 24 |
763670718 ps |
| T885 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.2687849166 |
|
|
May 07 03:35:52 PM PDT 24 |
May 07 03:40:55 PM PDT 24 |
3315706774 ps |
| T886 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.3088373584 |
|
|
May 07 03:37:03 PM PDT 24 |
May 07 04:06:19 PM PDT 24 |
112215802168 ps |
| T887 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.1943421177 |
|
|
May 07 03:33:02 PM PDT 24 |
May 07 03:35:12 PM PDT 24 |
1451198323 ps |
| T888 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.1510377292 |
|
|
May 07 03:36:19 PM PDT 24 |
May 07 03:36:22 PM PDT 24 |
39429426 ps |
| T889 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.2833866076 |
|
|
May 07 03:33:43 PM PDT 24 |
May 07 03:33:54 PM PDT 24 |
2000179452 ps |
| T890 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.418527926 |
|
|
May 07 03:37:15 PM PDT 24 |
May 07 03:37:16 PM PDT 24 |
26822219 ps |
| T891 |
/workspace/coverage/default/30.sram_ctrl_regwen.2824051676 |
|
|
May 07 03:34:55 PM PDT 24 |
May 07 03:36:30 PM PDT 24 |
6889689310 ps |
| T892 |
/workspace/coverage/default/31.sram_ctrl_bijection.2426269465 |
|
|
May 07 03:34:53 PM PDT 24 |
May 07 03:35:47 PM PDT 24 |
2577439124 ps |
| T893 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2777427158 |
|
|
May 07 03:32:59 PM PDT 24 |
May 07 03:33:24 PM PDT 24 |
609603727 ps |
| T894 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.1033925076 |
|
|
May 07 03:35:41 PM PDT 24 |
May 07 03:35:44 PM PDT 24 |
91536615 ps |
| T895 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2614700553 |
|
|
May 07 03:34:28 PM PDT 24 |
May 07 03:35:59 PM PDT 24 |
2525847715 ps |
| T896 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.442136370 |
|
|
May 07 03:35:00 PM PDT 24 |
May 07 03:35:01 PM PDT 24 |
29367372 ps |
| T897 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.4092720989 |
|
|
May 07 03:34:59 PM PDT 24 |
May 07 03:35:08 PM PDT 24 |
266256720 ps |
| T898 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.493160636 |
|
|
May 07 03:33:54 PM PDT 24 |
May 07 03:41:21 PM PDT 24 |
68737388662 ps |
| T899 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.2641082912 |
|
|
May 07 03:32:56 PM PDT 24 |
May 07 03:33:04 PM PDT 24 |
145249515 ps |
| T900 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.2000716578 |
|
|
May 07 03:32:58 PM PDT 24 |
May 07 03:33:00 PM PDT 24 |
88421523 ps |
| T901 |
/workspace/coverage/default/33.sram_ctrl_bijection.1283763389 |
|
|
May 07 03:35:13 PM PDT 24 |
May 07 03:36:01 PM PDT 24 |
10519943604 ps |
| T902 |
/workspace/coverage/default/25.sram_ctrl_smoke.387724244 |
|
|
May 07 03:34:23 PM PDT 24 |
May 07 03:34:31 PM PDT 24 |
302117767 ps |
| T903 |
/workspace/coverage/default/39.sram_ctrl_smoke.2790438768 |
|
|
May 07 03:35:52 PM PDT 24 |
May 07 03:36:08 PM PDT 24 |
500287140 ps |
| T904 |
/workspace/coverage/default/4.sram_ctrl_stress_all.2907280607 |
|
|
May 07 03:32:44 PM PDT 24 |
May 07 04:03:31 PM PDT 24 |
114838608976 ps |
| T905 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.2347631868 |
|
|
May 07 03:33:33 PM PDT 24 |
May 07 03:33:37 PM PDT 24 |
415076401 ps |
| T906 |
/workspace/coverage/default/0.sram_ctrl_regwen.2058548911 |
|
|
May 07 03:32:29 PM PDT 24 |
May 07 03:35:47 PM PDT 24 |
3625252791 ps |
| T907 |
/workspace/coverage/default/0.sram_ctrl_alert_test.3312414380 |
|
|
May 07 03:32:32 PM PDT 24 |
May 07 03:32:35 PM PDT 24 |
44228469 ps |
| T908 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.1386875350 |
|
|
May 07 03:32:33 PM PDT 24 |
May 07 03:59:57 PM PDT 24 |
66687366449 ps |
| T909 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.1705257716 |
|
|
May 07 03:35:34 PM PDT 24 |
May 07 03:43:21 PM PDT 24 |
50198914316 ps |
| T910 |
/workspace/coverage/default/13.sram_ctrl_bijection.3183224371 |
|
|
May 07 03:33:12 PM PDT 24 |
May 07 03:33:53 PM PDT 24 |
1920083686 ps |
| T911 |
/workspace/coverage/default/29.sram_ctrl_stress_all.3773411883 |
|
|
May 07 03:34:49 PM PDT 24 |
May 07 04:17:24 PM PDT 24 |
41748313994 ps |
| T912 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.310169850 |
|
|
May 07 03:34:35 PM PDT 24 |
May 07 03:34:36 PM PDT 24 |
85086152 ps |
| T913 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.1169623226 |
|
|
May 07 03:33:14 PM PDT 24 |
May 07 03:33:19 PM PDT 24 |
440427356 ps |
| T914 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2864435970 |
|
|
May 07 03:32:48 PM PDT 24 |
May 07 03:36:05 PM PDT 24 |
4142949937 ps |
| T915 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.464604180 |
|
|
May 07 03:35:46 PM PDT 24 |
May 07 03:35:52 PM PDT 24 |
85263808 ps |
| T916 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.2757318447 |
|
|
May 07 03:34:23 PM PDT 24 |
May 07 03:38:45 PM PDT 24 |
6587872046 ps |
| T917 |
/workspace/coverage/default/35.sram_ctrl_alert_test.3126456619 |
|
|
May 07 03:35:30 PM PDT 24 |
May 07 03:35:32 PM PDT 24 |
17917576 ps |
| T918 |
/workspace/coverage/default/22.sram_ctrl_bijection.2516225622 |
|
|
May 07 03:34:06 PM PDT 24 |
May 07 03:34:28 PM PDT 24 |
366279532 ps |
| T919 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.4132360132 |
|
|
May 07 03:33:05 PM PDT 24 |
May 07 03:38:43 PM PDT 24 |
6207434851 ps |
| T920 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.3494341890 |
|
|
May 07 03:35:29 PM PDT 24 |
May 07 03:52:25 PM PDT 24 |
43554163260 ps |
| T921 |
/workspace/coverage/default/39.sram_ctrl_partial_access.3481964393 |
|
|
May 07 03:35:57 PM PDT 24 |
May 07 03:36:32 PM PDT 24 |
665040291 ps |
| T922 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.4101627945 |
|
|
May 07 03:33:48 PM PDT 24 |
May 07 03:35:45 PM PDT 24 |
644509470 ps |
| T923 |
/workspace/coverage/default/37.sram_ctrl_bijection.3306780391 |
|
|
May 07 03:35:35 PM PDT 24 |
May 07 03:35:56 PM PDT 24 |
1339607944 ps |
| T924 |
/workspace/coverage/default/41.sram_ctrl_alert_test.1578731310 |
|
|
May 07 03:36:21 PM PDT 24 |
May 07 03:36:22 PM PDT 24 |
12296750 ps |
| T115 |
/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.1375737630 |
|
|
May 07 03:34:19 PM PDT 24 |
May 07 03:34:30 PM PDT 24 |
631180707 ps |
| T925 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.342406502 |
|
|
May 07 03:36:28 PM PDT 24 |
May 07 03:41:59 PM PDT 24 |
4816173714 ps |
| T926 |
/workspace/coverage/default/38.sram_ctrl_executable.2500400245 |
|
|
May 07 03:35:45 PM PDT 24 |
May 07 03:40:03 PM PDT 24 |
9305914848 ps |
| T927 |
/workspace/coverage/default/49.sram_ctrl_executable.3575868631 |
|
|
May 07 03:37:09 PM PDT 24 |
May 07 03:46:28 PM PDT 24 |
34824701180 ps |
| T928 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.4045067140 |
|
|
May 07 03:36:53 PM PDT 24 |
May 07 03:37:00 PM PDT 24 |
346058525 ps |
| T929 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.2442468516 |
|
|
May 07 03:36:20 PM PDT 24 |
May 07 03:53:23 PM PDT 24 |
66045958622 ps |
| T930 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.2656726686 |
|
|
May 07 03:36:23 PM PDT 24 |
May 07 03:36:26 PM PDT 24 |
631023048 ps |
| T931 |
/workspace/coverage/default/28.sram_ctrl_alert_test.2384633241 |
|
|
May 07 03:34:51 PM PDT 24 |
May 07 03:34:53 PM PDT 24 |
39837628 ps |
| T932 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.31015471 |
|
|
May 07 03:37:09 PM PDT 24 |
May 07 03:51:40 PM PDT 24 |
8708025157 ps |
| T104 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.635166376 |
|
|
May 07 03:29:22 PM PDT 24 |
May 07 03:29:23 PM PDT 24 |
37529154 ps |
| T66 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.228753754 |
|
|
May 07 03:28:52 PM PDT 24 |
May 07 03:28:57 PM PDT 24 |
6331913026 ps |
| T105 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3372181428 |
|
|
May 07 03:28:46 PM PDT 24 |
May 07 03:28:48 PM PDT 24 |
46217842 ps |
| T933 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1898983758 |
|
|
May 07 03:29:22 PM PDT 24 |
May 07 03:29:25 PM PDT 24 |
34787274 ps |
| T934 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.761450643 |
|
|
May 07 03:29:18 PM PDT 24 |
May 07 03:29:22 PM PDT 24 |
46107262 ps |
| T106 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.460076943 |
|
|
May 07 03:29:15 PM PDT 24 |
May 07 03:29:17 PM PDT 24 |
94406634 ps |
| T67 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3959677089 |
|
|
May 07 03:28:40 PM PDT 24 |
May 07 03:28:42 PM PDT 24 |
24725299 ps |
| T134 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.392369580 |
|
|
May 07 03:28:31 PM PDT 24 |
May 07 03:28:33 PM PDT 24 |
161175529 ps |
| T935 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2259944297 |
|
|
May 07 03:29:13 PM PDT 24 |
May 07 03:29:18 PM PDT 24 |
138469096 ps |
| T107 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.234722418 |
|
|
May 07 03:29:10 PM PDT 24 |
May 07 03:29:12 PM PDT 24 |
298887585 ps |
| T108 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3562443184 |
|
|
May 07 03:29:12 PM PDT 24 |
May 07 03:29:15 PM PDT 24 |
903992521 ps |
| T936 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1470741709 |
|
|
May 07 03:29:05 PM PDT 24 |
May 07 03:29:09 PM PDT 24 |
1424106481 ps |
| T68 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2830859188 |
|
|
May 07 03:29:16 PM PDT 24 |
May 07 03:29:20 PM PDT 24 |
398773941 ps |
| T937 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3234396057 |
|
|
May 07 03:29:20 PM PDT 24 |
May 07 03:29:22 PM PDT 24 |
25240657 ps |
| T69 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1257604642 |
|
|
May 07 03:29:01 PM PDT 24 |
May 07 03:29:06 PM PDT 24 |
2964093092 ps |
| T120 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2152776164 |
|
|
May 07 03:29:21 PM PDT 24 |
May 07 03:29:24 PM PDT 24 |
316953506 ps |
| T121 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1840197990 |
|
|
May 07 03:28:34 PM PDT 24 |
May 07 03:28:36 PM PDT 24 |
98733814 ps |
| T129 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3845129529 |
|
|
May 07 03:29:13 PM PDT 24 |
May 07 03:29:16 PM PDT 24 |
597993329 ps |
| T70 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3865969356 |
|
|
May 07 03:28:58 PM PDT 24 |
May 07 03:28:59 PM PDT 24 |
32130615 ps |
| T132 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3205962348 |
|
|
May 07 03:28:45 PM PDT 24 |
May 07 03:28:49 PM PDT 24 |
1440899766 ps |
| T938 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1574010884 |
|
|
May 07 03:29:21 PM PDT 24 |
May 07 03:29:26 PM PDT 24 |
476988886 ps |
| T96 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.690546203 |
|
|
May 07 03:29:00 PM PDT 24 |
May 07 03:29:01 PM PDT 24 |
16603997 ps |
| T939 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1706938216 |
|
|
May 07 03:28:32 PM PDT 24 |
May 07 03:28:37 PM PDT 24 |
462453112 ps |
| T97 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.868594774 |
|
|
May 07 03:28:44 PM PDT 24 |
May 07 03:28:48 PM PDT 24 |
1587175131 ps |
| T131 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1391074557 |
|
|
May 07 03:29:08 PM PDT 24 |
May 07 03:29:11 PM PDT 24 |
313126343 ps |
| T71 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.818564712 |
|
|
May 07 03:29:00 PM PDT 24 |
May 07 03:29:02 PM PDT 24 |
75225463 ps |
| T72 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.4140792537 |
|
|
May 07 03:28:52 PM PDT 24 |
May 07 03:28:53 PM PDT 24 |
33296691 ps |
| T940 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4290168645 |
|
|
May 07 03:29:08 PM PDT 24 |
May 07 03:29:13 PM PDT 24 |
1015539147 ps |
| T73 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2855352042 |
|
|
May 07 03:29:17 PM PDT 24 |
May 07 03:29:18 PM PDT 24 |
17655218 ps |
| T122 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.836684304 |
|
|
May 07 03:29:02 PM PDT 24 |
May 07 03:29:04 PM PDT 24 |
906216759 ps |
| T74 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.678997400 |
|
|
May 07 03:29:08 PM PDT 24 |
May 07 03:29:10 PM PDT 24 |
41923409 ps |
| T98 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.218183217 |
|
|
May 07 03:29:15 PM PDT 24 |
May 07 03:29:17 PM PDT 24 |
16838887 ps |
| T75 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1703760866 |
|
|
May 07 03:29:11 PM PDT 24 |
May 07 03:29:14 PM PDT 24 |
1076997183 ps |
| T127 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2324702840 |
|
|
May 07 03:28:31 PM PDT 24 |
May 07 03:28:34 PM PDT 24 |
597614112 ps |
| T941 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1755429923 |
|
|
May 07 03:29:13 PM PDT 24 |
May 07 03:29:18 PM PDT 24 |
120782988 ps |
| T942 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.803833300 |
|
|
May 07 03:29:16 PM PDT 24 |
May 07 03:29:18 PM PDT 24 |
11402590 ps |
| T77 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1241810835 |
|
|
May 07 03:29:21 PM PDT 24 |
May 07 03:29:25 PM PDT 24 |
3426712328 ps |
| T943 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.308158499 |
|
|
May 07 03:28:51 PM PDT 24 |
May 07 03:28:56 PM PDT 24 |
509234760 ps |
| T133 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.727443005 |
|
|
May 07 03:28:50 PM PDT 24 |
May 07 03:28:53 PM PDT 24 |
186622797 ps |
| T78 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.4171772320 |
|
|
May 07 03:29:03 PM PDT 24 |
May 07 03:29:05 PM PDT 24 |
14779381 ps |
| T944 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1576223348 |
|
|
May 07 03:29:22 PM PDT 24 |
May 07 03:29:28 PM PDT 24 |
644235455 ps |
| T945 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1350279666 |
|
|
May 07 03:28:47 PM PDT 24 |
May 07 03:28:48 PM PDT 24 |
19389256 ps |
| T79 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.754918863 |
|
|
May 07 03:28:46 PM PDT 24 |
May 07 03:28:49 PM PDT 24 |
1784668900 ps |
| T946 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1684956134 |
|
|
May 07 03:28:36 PM PDT 24 |
May 07 03:28:40 PM PDT 24 |
379720296 ps |
| T947 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2033497123 |
|
|
May 07 03:28:38 PM PDT 24 |
May 07 03:28:39 PM PDT 24 |
23237645 ps |
| T948 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2368036420 |
|
|
May 07 03:29:12 PM PDT 24 |
May 07 03:29:14 PM PDT 24 |
30930205 ps |
| T949 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1893577094 |
|
|
May 07 03:29:16 PM PDT 24 |
May 07 03:29:17 PM PDT 24 |
24401605 ps |
| T950 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1879780356 |
|
|
May 07 03:29:07 PM PDT 24 |
May 07 03:29:09 PM PDT 24 |
14194831 ps |
| T951 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.393477951 |
|
|
May 07 03:29:13 PM PDT 24 |
May 07 03:29:15 PM PDT 24 |
69832779 ps |
| T952 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1934345306 |
|
|
May 07 03:29:11 PM PDT 24 |
May 07 03:29:14 PM PDT 24 |
118236933 ps |
| T953 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.319866628 |
|
|
May 07 03:28:45 PM PDT 24 |
May 07 03:28:47 PM PDT 24 |
15028152 ps |
| T954 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.114070013 |
|
|
May 07 03:28:52 PM PDT 24 |
May 07 03:28:55 PM PDT 24 |
439723959 ps |
| T130 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.543670561 |
|
|
May 07 03:28:41 PM PDT 24 |
May 07 03:28:44 PM PDT 24 |
158406098 ps |
| T955 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1833260875 |
|
|
May 07 03:29:06 PM PDT 24 |
May 07 03:29:10 PM PDT 24 |
65854200 ps |
| T956 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.877577236 |
|
|
May 07 03:28:47 PM PDT 24 |
May 07 03:28:48 PM PDT 24 |
162456820 ps |
| T957 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1714086572 |
|
|
May 07 03:28:57 PM PDT 24 |
May 07 03:29:00 PM PDT 24 |
80604408 ps |
| T958 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.730754095 |
|
|
May 07 03:29:12 PM PDT 24 |
May 07 03:29:14 PM PDT 24 |
262326816 ps |
| T959 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1727263082 |
|
|
May 07 03:28:58 PM PDT 24 |
May 07 03:29:00 PM PDT 24 |
142779434 ps |
| T960 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.552825019 |
|
|
May 07 03:28:42 PM PDT 24 |
May 07 03:28:43 PM PDT 24 |
45942368 ps |
| T961 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.436314086 |
|
|
May 07 03:29:21 PM PDT 24 |
May 07 03:29:23 PM PDT 24 |
44579745 ps |
| T126 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3683493539 |
|
|
May 07 03:29:13 PM PDT 24 |
May 07 03:29:16 PM PDT 24 |
520864873 ps |
| T89 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3269153938 |
|
|
May 07 03:29:17 PM PDT 24 |
May 07 03:29:19 PM PDT 24 |
45279253 ps |
| T80 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2941472044 |
|
|
May 07 03:28:41 PM PDT 24 |
May 07 03:28:42 PM PDT 24 |
19029516 ps |
| T962 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1612208114 |
|
|
May 07 03:28:44 PM PDT 24 |
May 07 03:28:45 PM PDT 24 |
59233141 ps |
| T81 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.218720180 |
|
|
May 07 03:28:40 PM PDT 24 |
May 07 03:28:44 PM PDT 24 |
844745340 ps |
| T124 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.415309339 |
|
|
May 07 03:29:21 PM PDT 24 |
May 07 03:29:23 PM PDT 24 |
114993845 ps |
| T963 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.315869560 |
|
|
May 07 03:29:02 PM PDT 24 |
May 07 03:29:03 PM PDT 24 |
110475379 ps |
| T964 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1566095815 |
|
|
May 07 03:29:22 PM PDT 24 |
May 07 03:29:24 PM PDT 24 |
29059774 ps |
| T965 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2655346506 |
|
|
May 07 03:28:51 PM PDT 24 |
May 07 03:28:53 PM PDT 24 |
22980703 ps |
| T966 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3957711957 |
|
|
May 07 03:29:03 PM PDT 24 |
May 07 03:29:05 PM PDT 24 |
62104377 ps |
| T90 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3232412394 |
|
|
May 07 03:29:12 PM PDT 24 |
May 07 03:29:13 PM PDT 24 |
25500693 ps |
| T967 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2515237760 |
|
|
May 07 03:29:03 PM PDT 24 |
May 07 03:29:05 PM PDT 24 |
17890733 ps |
| T968 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3644869765 |
|
|
May 07 03:29:06 PM PDT 24 |
May 07 03:29:09 PM PDT 24 |
94167641 ps |
| T969 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1076014571 |
|
|
May 07 03:29:11 PM PDT 24 |
May 07 03:29:13 PM PDT 24 |
11301203 ps |
| T970 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3007709031 |
|
|
May 07 03:29:07 PM PDT 24 |
May 07 03:29:09 PM PDT 24 |
11982772 ps |
| T971 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2308564523 |
|
|
May 07 03:29:11 PM PDT 24 |
May 07 03:29:17 PM PDT 24 |
261752718 ps |
| T91 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3656207712 |
|
|
May 07 03:29:00 PM PDT 24 |
May 07 03:29:05 PM PDT 24 |
1561229612 ps |
| T972 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3082210063 |
|
|
May 07 03:29:16 PM PDT 24 |
May 07 03:29:18 PM PDT 24 |
17784847 ps |
| T973 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1648070701 |
|
|
May 07 03:28:40 PM PDT 24 |
May 07 03:28:42 PM PDT 24 |
122825859 ps |
| T92 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2007702485 |
|
|
May 07 03:29:20 PM PDT 24 |
May 07 03:29:21 PM PDT 24 |
13664902 ps |
| T974 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2278863835 |
|
|
May 07 03:28:40 PM PDT 24 |
May 07 03:28:41 PM PDT 24 |
34123881 ps |
| T975 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2849093769 |
|
|
May 07 03:29:10 PM PDT 24 |
May 07 03:29:13 PM PDT 24 |
234042587 ps |
| T976 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2378965361 |
|
|
May 07 03:29:17 PM PDT 24 |
May 07 03:29:19 PM PDT 24 |
160927215 ps |
| T977 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1752722448 |
|
|
May 07 03:28:44 PM PDT 24 |
May 07 03:28:46 PM PDT 24 |
312377672 ps |
| T978 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1213308752 |
|
|
May 07 03:28:50 PM PDT 24 |
May 07 03:28:52 PM PDT 24 |
74800513 ps |
| T123 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3727811713 |
|
|
May 07 03:29:08 PM PDT 24 |
May 07 03:29:12 PM PDT 24 |
1047758825 ps |
| T979 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2668622955 |
|
|
May 07 03:28:56 PM PDT 24 |
May 07 03:28:59 PM PDT 24 |
425832477 ps |
| T93 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3601384764 |
|
|
May 07 03:29:12 PM PDT 24 |
May 07 03:29:16 PM PDT 24 |
361973267 ps |
| T980 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2060476936 |
|
|
May 07 03:28:32 PM PDT 24 |
May 07 03:28:36 PM PDT 24 |
1836680879 ps |
| T128 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3599675637 |
|
|
May 07 03:29:03 PM PDT 24 |
May 07 03:29:06 PM PDT 24 |
317726704 ps |
| T981 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.898969934 |
|
|
May 07 03:28:31 PM PDT 24 |
May 07 03:28:32 PM PDT 24 |
22795399 ps |
| T982 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.4063178607 |
|
|
May 07 03:29:16 PM PDT 24 |
May 07 03:29:18 PM PDT 24 |
88943619 ps |
| T983 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2316683823 |
|
|
May 07 03:28:42 PM PDT 24 |
May 07 03:28:45 PM PDT 24 |
134292228 ps |
| T984 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.4072292420 |
|
|
May 07 03:29:01 PM PDT 24 |
May 07 03:29:03 PM PDT 24 |
199161287 ps |
| T985 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1421349962 |
|
|
May 07 03:28:44 PM PDT 24 |
May 07 03:28:47 PM PDT 24 |
24103355 ps |
| T986 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2242508618 |
|
|
May 07 03:28:52 PM PDT 24 |
May 07 03:28:57 PM PDT 24 |
680870175 ps |
| T987 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3144905335 |
|
|
May 07 03:29:22 PM PDT 24 |
May 07 03:29:26 PM PDT 24 |
1534657599 ps |
| T988 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.715677858 |
|
|
May 07 03:28:36 PM PDT 24 |
May 07 03:28:38 PM PDT 24 |
20786910 ps |
| T989 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2130890458 |
|
|
May 07 03:29:09 PM PDT 24 |
May 07 03:29:15 PM PDT 24 |
484042459 ps |
| T990 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2911883882 |
|
|
May 07 03:28:58 PM PDT 24 |
May 07 03:29:00 PM PDT 24 |
92903176 ps |
| T991 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3837142696 |
|
|
May 07 03:28:32 PM PDT 24 |
May 07 03:28:33 PM PDT 24 |
41462803 ps |
| T992 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.83811822 |
|
|
May 07 03:29:18 PM PDT 24 |
May 07 03:29:21 PM PDT 24 |
128385912 ps |
| T993 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3812637961 |
|
|
May 07 03:29:24 PM PDT 24 |
May 07 03:29:25 PM PDT 24 |
53288540 ps |
| T994 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.761966215 |
|
|
May 07 03:29:06 PM PDT 24 |
May 07 03:29:09 PM PDT 24 |
256603774 ps |
| T995 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3839613860 |
|
|
May 07 03:29:07 PM PDT 24 |
May 07 03:29:10 PM PDT 24 |
302204259 ps |
| T996 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.4071846106 |
|
|
May 07 03:29:22 PM PDT 24 |
May 07 03:29:24 PM PDT 24 |
31860829 ps |
| T997 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3749386279 |
|
|
May 07 03:28:51 PM PDT 24 |
May 07 03:28:53 PM PDT 24 |
18697121 ps |
| T94 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.521698099 |
|
|
May 07 03:28:50 PM PDT 24 |
May 07 03:28:52 PM PDT 24 |
159192158 ps |
| T998 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2442503315 |
|
|
May 07 03:28:35 PM PDT 24 |
May 07 03:28:36 PM PDT 24 |
12612966 ps |
| T125 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3591267258 |
|
|
May 07 03:29:23 PM PDT 24 |
May 07 03:29:26 PM PDT 24 |
433967520 ps |
| T999 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4191838816 |
|
|
May 07 03:28:31 PM PDT 24 |
May 07 03:28:33 PM PDT 24 |
26561807 ps |
| T1000 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2329134362 |
|
|
May 07 03:29:05 PM PDT 24 |
May 07 03:29:07 PM PDT 24 |
299797313 ps |
| T1001 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3749584755 |
|
|
May 07 03:28:44 PM PDT 24 |
May 07 03:28:46 PM PDT 24 |
55046375 ps |