Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	141929958	1			T1	12284		T2	355412		T3	376090
instr_valid_dis	111608051	1			T1	12284		T3	376090		T4	686916
instr_en	19845361	1			T2	355412		T7	161460		T13	37262

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9387914	1			T2	56976		T7	97102		T13	36162
sram_ifetch_valid_disable	113077869	1			T1	12284		T2	196682		T3	376090
sram_ifetch_enable	19464175	1			T2	101754		T7	170212		T13	20342

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	141929958	1			T1	12284		T2	355412		T3	376090
hw_debug_en_valid_off	111082025	1			T1	12284		T2	111038		T3	376090
hw_debug_en_on	20305091	1			T2	14414		T7	190768		T13	20342

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	113077869	1			T1	12284		T2	196682		T3	376090
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	100060466	1			T1	12284		T3	376090		T4	686916
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8345806	1			T2	196682		T7	44564		T13	16920
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3848106	1			T2	56976		T7	46870		T13	36162
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1575166	1			T27	31170		T42	18102		T128	62552
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1493154	1			T2	56976		T7	13302		T51	16632
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3521892	1			T7	50232		T27	5064		T127	1600
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1517054	1			T7	39906		T27	5064		T127	1600
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1531198	1			T7	10326		T52	185824		T42	25576
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8799369	1			T2	12840		T7	126916		T51	14852
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2919010	1			T7	28174		T27	58290		T127	8612
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3434616	1			T2	12840		T7	44564		T51	14852

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	7459809	1			T2	101754		T7	93268		T13	20342
lc_exec_en	7983830	1			T2	1574		T7	13620		T13	20342
valid_exec_dis	107696829	1			T1	12284		T2	17374		T3	376090
invalid_exec_dis	28852089	1			T2	158730		T7	267314		T13	56504