Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.08	99.81	96.99	100.00	100.00	98.57	99.70	98.52

Total tests in report: 1024

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
87.13	87.13	97.76	97.76	82.47	82.47	93.71	93.71	71.43	71.43	90.49	90.49	95.05	95.05	79.04	79.04	/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2547852523
93.31	6.18	99.12	1.36	87.01	4.55	94.53	0.82	100.00	28.57	95.10	4.61	95.05	0.00	82.37	3.34	/workspace/coverage/default/19.sram_ctrl_lc_escalation.3812168888
94.55	1.24	99.51	0.39	89.61	2.60	96.49	1.97	100.00	0.00	97.12	2.02	95.80	0.75	83.30	0.93	/workspace/coverage/default/3.sram_ctrl_sec_cm.1859580567
95.64	1.09	99.71	0.19	92.60	2.99	96.49	0.00	100.00	0.00	98.85	1.73	95.95	0.15	85.90	2.60	/workspace/coverage/default/1.sram_ctrl_regwen.2357028415
96.39	0.74	99.71	0.00	92.99	0.39	96.49	0.00	100.00	0.00	98.85	0.00	95.95	0.00	90.72	4.82	/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3898343421
96.88	0.49	99.71	0.00	93.12	0.13	96.49	0.00	100.00	0.00	98.85	0.00	96.85	0.90	93.14	2.41	/workspace/coverage/default/40.sram_ctrl_stress_all.715175928
97.23	0.35	99.71	0.00	93.25	0.13	97.89	1.39	100.00	0.00	98.85	0.00	97.75	0.90	93.14	0.00	/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2318258877
97.52	0.29	99.71	0.00	93.51	0.26	97.96	0.07	100.00	0.00	98.85	0.00	99.10	1.35	93.51	0.37	/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2041361288
97.78	0.27	99.71	0.00	93.51	0.00	97.96	0.00	100.00	0.00	98.85	0.00	99.10	0.00	95.36	1.86	/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1894435581
97.99	0.20	99.71	0.00	93.64	0.13	97.96	0.00	100.00	0.00	98.85	0.00	99.10	0.00	96.66	1.30	/workspace/coverage/default/16.sram_ctrl_stress_all.86535551
98.18	0.19	99.71	0.00	93.64	0.00	98.78	0.82	100.00	0.00	98.85	0.00	99.25	0.15	97.03	0.37	/workspace/coverage/default/0.sram_ctrl_stress_pipeline.846725477
98.30	0.12	99.81	0.10	93.64	0.00	99.54	0.75	100.00	0.00	98.85	0.00	99.25	0.00	97.03	0.00	/workspace/coverage/default/42.sram_ctrl_ram_cfg.843737536
98.39	0.09	99.81	0.00	93.64	0.00	99.54	0.00	100.00	0.00	98.85	0.00	99.70	0.45	97.22	0.19	/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2080008510
98.47	0.08	99.81	0.00	93.64	0.00	99.54	0.00	100.00	0.00	98.85	0.00	99.70	0.00	97.77	0.56	/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1179617873
98.54	0.07	99.81	0.00	93.77	0.13	99.89	0.36	100.00	0.00	98.85	0.00	99.70	0.00	97.77	0.00	/workspace/coverage/default/31.sram_ctrl_stress_all.3654831050
98.61	0.07	99.81	0.00	94.16	0.39	99.96	0.07	100.00	0.00	98.85	0.00	99.70	0.00	97.77	0.00	/workspace/coverage/default/1.sram_ctrl_alert_test.645840807
98.66	0.05	99.81	0.00	94.16	0.00	99.96	0.00	100.00	0.00	98.85	0.00	99.70	0.00	98.14	0.37	/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.400013639
98.69	0.03	99.81	0.00	94.16	0.00	99.96	0.00	100.00	0.00	98.85	0.00	99.70	0.00	98.33	0.19	/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1658613303
98.71	0.03	99.81	0.00	94.16	0.00	99.96	0.00	100.00	0.00	98.85	0.00	99.70	0.00	98.52	0.19	/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1210823118
98.72	0.01	99.81	0.00	94.16	0.00	100.00	0.04	100.00	0.00	98.85	0.00	99.70	0.00	98.52	0.00	/workspace/coverage/default/15.sram_ctrl_regwen.1166729498

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.249901504
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.225148577
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2551577162
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3395782426
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3585259552
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.4279106789
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.510288780
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.790119471
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1454159918
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2783623090
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3302848865
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.505398822
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.337661690
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4063550814
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3376200034
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3058747332
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1224642771
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.736924267
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.767609514
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3938173894
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3782377739
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2947843452
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2294387605
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3793621664
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1850701361
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.808808661
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2831378956
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.4186186970
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3750694835
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4190469533
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.329344836
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2485584305
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.835817237
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1556889406
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.464827214
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1144944819
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3602653609
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2854946198
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2405069314
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1338653414
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3255857482
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1040500349
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.468642721
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.544275980
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1482702824
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.770057114
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3018587650
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.32682290
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3134312913
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3321703186
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3270149359
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3876451534
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2746028776
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3643379359
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1323012952
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2387135505
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.409913606
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3587617518
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3487369258
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2078873650
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3003315615
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.958146018
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.4191570111
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.790441451
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.525862894
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.675294949
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3597494829
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3038804761
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3326449027
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2355204008
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.952602998
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.91775400
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.932878714
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2215395365
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.859502953
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.805527495
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.928726001
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3913116390
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2157107397
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.4023850140
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2224766200
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1023297501
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2730929917
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3015938206
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2431216741
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3182296654
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2928432410
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2505945735
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2916635847
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2456245930
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.824104581
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.313883850
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.63319071
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2048846321
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1119245928
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3091570676
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2900778944
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3499556856
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1966430081
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3256080727
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3787445688
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2053121180
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4178877424
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3284745162
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1647102257
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2084583980
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1160473271
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2112216810
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.721209347
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1614080206
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2727847395
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3107283988
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2284824939
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3628631774
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3821999554
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1764639160
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1818693976
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2372672949
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1778193976
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.967620214
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2586859165
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3169282671
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1451384475
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2283663233
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.629529204
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1229685215
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.32730746
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2647058268
/workspace/coverage/default/0.sram_ctrl_alert_test.4153391107
/workspace/coverage/default/0.sram_ctrl_bijection.2204098943
/workspace/coverage/default/0.sram_ctrl_executable.102487886
/workspace/coverage/default/0.sram_ctrl_lc_escalation.217001350
/workspace/coverage/default/0.sram_ctrl_max_throughput.3946198882
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1631297982
/workspace/coverage/default/0.sram_ctrl_mem_walk.2382229674
/workspace/coverage/default/0.sram_ctrl_multiple_keys.4000283995
/workspace/coverage/default/0.sram_ctrl_partial_access.970253419
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2168527347
/workspace/coverage/default/0.sram_ctrl_ram_cfg.2485815382
/workspace/coverage/default/0.sram_ctrl_regwen.2215921099
/workspace/coverage/default/0.sram_ctrl_sec_cm.373363808
/workspace/coverage/default/0.sram_ctrl_smoke.163172810
/workspace/coverage/default/0.sram_ctrl_stress_all.982388320
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3151511688
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.4291348237
/workspace/coverage/default/1.sram_ctrl_bijection.236153347
/workspace/coverage/default/1.sram_ctrl_executable.1724357640
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3763844302
/workspace/coverage/default/1.sram_ctrl_max_throughput.4113645156
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.243168784
/workspace/coverage/default/1.sram_ctrl_mem_walk.3203220968
/workspace/coverage/default/1.sram_ctrl_multiple_keys.3201834982
/workspace/coverage/default/1.sram_ctrl_partial_access.4172815233
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1130790203
/workspace/coverage/default/1.sram_ctrl_ram_cfg.923817236
/workspace/coverage/default/1.sram_ctrl_sec_cm.727201005
/workspace/coverage/default/1.sram_ctrl_smoke.2564201953
/workspace/coverage/default/1.sram_ctrl_stress_all.1559966920
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.252289999
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.4058128304
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1283654929
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.1280934664
/workspace/coverage/default/10.sram_ctrl_alert_test.216141112
/workspace/coverage/default/10.sram_ctrl_bijection.3555766445
/workspace/coverage/default/10.sram_ctrl_executable.3452780647
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3134468282
/workspace/coverage/default/10.sram_ctrl_max_throughput.153861166
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.1935172184
/workspace/coverage/default/10.sram_ctrl_mem_walk.3317050402
/workspace/coverage/default/10.sram_ctrl_multiple_keys.1850455965
/workspace/coverage/default/10.sram_ctrl_partial_access.711201291
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3383335515
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1524002905
/workspace/coverage/default/10.sram_ctrl_regwen.4112112665
/workspace/coverage/default/10.sram_ctrl_smoke.3752235757
/workspace/coverage/default/10.sram_ctrl_stress_all.4268233071
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3349002464
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.4151312481
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1337485417
/workspace/coverage/default/11.sram_ctrl_alert_test.1309015738
/workspace/coverage/default/11.sram_ctrl_bijection.3467203825
/workspace/coverage/default/11.sram_ctrl_executable.1152700454
/workspace/coverage/default/11.sram_ctrl_lc_escalation.3040345469
/workspace/coverage/default/11.sram_ctrl_max_throughput.3826697223
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.4060936431
/workspace/coverage/default/11.sram_ctrl_mem_walk.2077220640
/workspace/coverage/default/11.sram_ctrl_multiple_keys.1611751848
/workspace/coverage/default/11.sram_ctrl_partial_access.2549413265
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3625342990
/workspace/coverage/default/11.sram_ctrl_ram_cfg.195176279
/workspace/coverage/default/11.sram_ctrl_regwen.1801013946
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/workspace/coverage/default/42.sram_ctrl_regwen.3840535372
/workspace/coverage/default/42.sram_ctrl_smoke.483445673
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3764068813
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.2955964121
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.635136639
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.4267715658
/workspace/coverage/default/43.sram_ctrl_alert_test.4147217907
/workspace/coverage/default/43.sram_ctrl_bijection.97990610
/workspace/coverage/default/43.sram_ctrl_executable.4097437747
/workspace/coverage/default/43.sram_ctrl_lc_escalation.4134044376
/workspace/coverage/default/43.sram_ctrl_max_throughput.2490829342
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.3825555031
/workspace/coverage/default/43.sram_ctrl_mem_walk.988103524
/workspace/coverage/default/43.sram_ctrl_multiple_keys.757765257
/workspace/coverage/default/43.sram_ctrl_partial_access.225539054
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1983163340
/workspace/coverage/default/43.sram_ctrl_ram_cfg.2100527728
/workspace/coverage/default/43.sram_ctrl_regwen.1455360991
/workspace/coverage/default/43.sram_ctrl_smoke.3470652369
/workspace/coverage/default/43.sram_ctrl_stress_all.3395931576
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.117666677
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.1436388205
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.802206547
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.4083561267
/workspace/coverage/default/44.sram_ctrl_alert_test.2467800354
/workspace/coverage/default/44.sram_ctrl_bijection.3545033849
/workspace/coverage/default/44.sram_ctrl_executable.3598582721
/workspace/coverage/default/44.sram_ctrl_lc_escalation.2355919157
/workspace/coverage/default/44.sram_ctrl_max_throughput.2603955215
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.1465966959
/workspace/coverage/default/44.sram_ctrl_mem_walk.2258097037
/workspace/coverage/default/44.sram_ctrl_multiple_keys.433911668
/workspace/coverage/default/44.sram_ctrl_partial_access.3935965481
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2306587231
/workspace/coverage/default/44.sram_ctrl_ram_cfg.3325404607
/workspace/coverage/default/44.sram_ctrl_regwen.2405345797
/workspace/coverage/default/44.sram_ctrl_smoke.2849774197
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1709501703
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.3100765672
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3704612257
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.477129900
/workspace/coverage/default/45.sram_ctrl_alert_test.636898110
/workspace/coverage/default/45.sram_ctrl_bijection.1538366713
/workspace/coverage/default/45.sram_ctrl_executable.2572097223
/workspace/coverage/default/45.sram_ctrl_lc_escalation.3684804764
/workspace/coverage/default/45.sram_ctrl_max_throughput.2203013961
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.528968978
/workspace/coverage/default/45.sram_ctrl_mem_walk.4202516140
/workspace/coverage/default/45.sram_ctrl_multiple_keys.4207426712
/workspace/coverage/default/45.sram_ctrl_partial_access.2650524752
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1911005598
/workspace/coverage/default/45.sram_ctrl_ram_cfg.936023315
/workspace/coverage/default/45.sram_ctrl_regwen.1778741191
/workspace/coverage/default/45.sram_ctrl_smoke.3495550736
/workspace/coverage/default/45.sram_ctrl_stress_all.3713075787
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3676373077
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3193401922
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.4086552175
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.3796326464
/workspace/coverage/default/46.sram_ctrl_alert_test.643108378
/workspace/coverage/default/46.sram_ctrl_bijection.1283367026
/workspace/coverage/default/46.sram_ctrl_executable.2664497221
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1361724642
/workspace/coverage/default/46.sram_ctrl_max_throughput.4001676494
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.3536635553
/workspace/coverage/default/46.sram_ctrl_mem_walk.3533902304
/workspace/coverage/default/46.sram_ctrl_multiple_keys.1780301331
/workspace/coverage/default/46.sram_ctrl_partial_access.3524931290
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.223690304
/workspace/coverage/default/46.sram_ctrl_ram_cfg.2364830431
/workspace/coverage/default/46.sram_ctrl_regwen.1268233234
/workspace/coverage/default/46.sram_ctrl_smoke.3887601838
/workspace/coverage/default/46.sram_ctrl_stress_all.3747559610
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1317668861
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.2684956695
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3595115603
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.1329799717
/workspace/coverage/default/47.sram_ctrl_alert_test.3432568583
/workspace/coverage/default/47.sram_ctrl_bijection.3124937522
/workspace/coverage/default/47.sram_ctrl_executable.1719578024
/workspace/coverage/default/47.sram_ctrl_lc_escalation.2371591873
/workspace/coverage/default/47.sram_ctrl_max_throughput.1017207228
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.2122859971
/workspace/coverage/default/47.sram_ctrl_mem_walk.683676329
/workspace/coverage/default/47.sram_ctrl_multiple_keys.2143941358
/workspace/coverage/default/47.sram_ctrl_partial_access.1087124566
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1817215280
/workspace/coverage/default/47.sram_ctrl_ram_cfg.3197782660
/workspace/coverage/default/47.sram_ctrl_regwen.2508700463
/workspace/coverage/default/47.sram_ctrl_smoke.501483634
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2161430403
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.1984877684
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3341027243
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.1919287744
/workspace/coverage/default/48.sram_ctrl_alert_test.2322295246
/workspace/coverage/default/48.sram_ctrl_bijection.4110785896
/workspace/coverage/default/48.sram_ctrl_executable.583140638
/workspace/coverage/default/48.sram_ctrl_lc_escalation.1602406490
/workspace/coverage/default/48.sram_ctrl_max_throughput.1873305726
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2687894858
/workspace/coverage/default/48.sram_ctrl_mem_walk.309672942
/workspace/coverage/default/48.sram_ctrl_multiple_keys.534363549
/workspace/coverage/default/48.sram_ctrl_partial_access.450911484
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3262751139
/workspace/coverage/default/48.sram_ctrl_ram_cfg.2769742763
/workspace/coverage/default/48.sram_ctrl_regwen.1275803292
/workspace/coverage/default/48.sram_ctrl_smoke.792100518
/workspace/coverage/default/48.sram_ctrl_stress_all.1509395665
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3457264384
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.968239078
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1475906438
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.1569394627
/workspace/coverage/default/49.sram_ctrl_alert_test.3887988874
/workspace/coverage/default/49.sram_ctrl_bijection.456543758
/workspace/coverage/default/49.sram_ctrl_executable.1082521221
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2282373971
/workspace/coverage/default/49.sram_ctrl_max_throughput.335871176
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2373208086
/workspace/coverage/default/49.sram_ctrl_mem_walk.2145898486
/workspace/coverage/default/49.sram_ctrl_multiple_keys.2451587669
/workspace/coverage/default/49.sram_ctrl_partial_access.2204883186
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1532750171
/workspace/coverage/default/49.sram_ctrl_ram_cfg.118070005
/workspace/coverage/default/49.sram_ctrl_regwen.286460993
/workspace/coverage/default/49.sram_ctrl_smoke.3993823047
/workspace/coverage/default/49.sram_ctrl_stress_all.1772229395
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1216472895
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2970160434
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3465490427
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.2584947195
/workspace/coverage/default/5.sram_ctrl_alert_test.1715977776
/workspace/coverage/default/5.sram_ctrl_bijection.111944933
/workspace/coverage/default/5.sram_ctrl_executable.2955836278
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2849351445
/workspace/coverage/default/5.sram_ctrl_max_throughput.573096759
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3061102105
/workspace/coverage/default/5.sram_ctrl_mem_walk.2456682072
/workspace/coverage/default/5.sram_ctrl_multiple_keys.772820106
/workspace/coverage/default/5.sram_ctrl_partial_access.3914710873
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2958928923
/workspace/coverage/default/5.sram_ctrl_ram_cfg.895720566
/workspace/coverage/default/5.sram_ctrl_regwen.1225825571
/workspace/coverage/default/5.sram_ctrl_smoke.2574109567
/workspace/coverage/default/5.sram_ctrl_stress_all.579758349
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.4137865558
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.914210420
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.391509303
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.985740500
/workspace/coverage/default/6.sram_ctrl_alert_test.2248628525
/workspace/coverage/default/6.sram_ctrl_bijection.1669270185
/workspace/coverage/default/6.sram_ctrl_executable.3799084480
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2097887309
/workspace/coverage/default/6.sram_ctrl_max_throughput.2825906970
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1409383364
/workspace/coverage/default/6.sram_ctrl_mem_walk.505269146
/workspace/coverage/default/6.sram_ctrl_multiple_keys.2695867276
/workspace/coverage/default/6.sram_ctrl_partial_access.687474080
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.582084183
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1073465226
/workspace/coverage/default/6.sram_ctrl_regwen.657892728
/workspace/coverage/default/6.sram_ctrl_smoke.2471639679
/workspace/coverage/default/6.sram_ctrl_stress_all.3485360858
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2601765328
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2735242852
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1093100699
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.733821391
/workspace/coverage/default/7.sram_ctrl_alert_test.2515174777
/workspace/coverage/default/7.sram_ctrl_bijection.2306238907
/workspace/coverage/default/7.sram_ctrl_executable.3736290413
/workspace/coverage/default/7.sram_ctrl_lc_escalation.3693879590
/workspace/coverage/default/7.sram_ctrl_max_throughput.63219503
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3696967346
/workspace/coverage/default/7.sram_ctrl_mem_walk.2852506166
/workspace/coverage/default/7.sram_ctrl_multiple_keys.1115355654
/workspace/coverage/default/7.sram_ctrl_partial_access.3608304822
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.28868044
/workspace/coverage/default/7.sram_ctrl_ram_cfg.81658010
/workspace/coverage/default/7.sram_ctrl_regwen.460990807
/workspace/coverage/default/7.sram_ctrl_smoke.2442867571
/workspace/coverage/default/7.sram_ctrl_stress_all.2047174322
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1892855640
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2649038397
/workspace/coverage/default/8.sram_ctrl_alert_test.3736817763
/workspace/coverage/default/8.sram_ctrl_bijection.971308878
/workspace/coverage/default/8.sram_ctrl_executable.3401261273
/workspace/coverage/default/8.sram_ctrl_lc_escalation.1275360852
/workspace/coverage/default/8.sram_ctrl_max_throughput.2855482132
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.63317223
/workspace/coverage/default/8.sram_ctrl_mem_walk.4145167319
/workspace/coverage/default/8.sram_ctrl_multiple_keys.481864069
/workspace/coverage/default/8.sram_ctrl_partial_access.3726857463
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1569968860
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3323567795
/workspace/coverage/default/8.sram_ctrl_regwen.3691566252
/workspace/coverage/default/8.sram_ctrl_smoke.1303142612
/workspace/coverage/default/8.sram_ctrl_stress_all.270485863
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1672204011
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.95144288
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.398585810
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.2242758762
/workspace/coverage/default/9.sram_ctrl_alert_test.3600016793
/workspace/coverage/default/9.sram_ctrl_bijection.3288070038
/workspace/coverage/default/9.sram_ctrl_executable.581654501
/workspace/coverage/default/9.sram_ctrl_lc_escalation.268394717
/workspace/coverage/default/9.sram_ctrl_max_throughput.3835114646
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.3708667859
/workspace/coverage/default/9.sram_ctrl_mem_walk.1162258231
/workspace/coverage/default/9.sram_ctrl_multiple_keys.1190499871
/workspace/coverage/default/9.sram_ctrl_partial_access.2993455148
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3636214720
/workspace/coverage/default/9.sram_ctrl_ram_cfg.961035340
/workspace/coverage/default/9.sram_ctrl_regwen.1891736065
/workspace/coverage/default/9.sram_ctrl_smoke.2520513305
/workspace/coverage/default/9.sram_ctrl_stress_all.2050224697
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.816206056
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1565730506
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3713541495

Total test records in report: 1024

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/15.sram_ctrl_mem_walk.3298260928	May 09 12:41:50 PM PDT 24	May 09 12:42:03 PM PDT 24	551351426 ps
T2	/workspace/coverage/default/38.sram_ctrl_regwen.3345405762	May 09 12:43:57 PM PDT 24	May 09 12:53:32 PM PDT 24	7939499301 ps
T3	/workspace/coverage/default/18.sram_ctrl_stress_pipeline.430616661	May 09 12:42:03 PM PDT 24	May 09 12:45:42 PM PDT 24	9129166618 ps
T4	/workspace/coverage/default/21.sram_ctrl_stress_pipeline.1293079292	May 09 12:42:12 PM PDT 24	May 09 12:49:10 PM PDT 24	20592844234 ps
T7	/workspace/coverage/default/40.sram_ctrl_stress_all.715175928	May 09 12:44:15 PM PDT 24	May 09 01:11:48 PM PDT 24	4818488574 ps
T5	/workspace/coverage/default/5.sram_ctrl_partial_access.3914710873	May 09 12:41:07 PM PDT 24	May 09 12:41:18 PM PDT 24	4493821618 ps
T10	/workspace/coverage/default/21.sram_ctrl_access_during_key_req.199783995	May 09 12:42:21 PM PDT 24	May 09 12:55:47 PM PDT 24	3202496029 ps
T11	/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2318258877	May 09 12:41:19 PM PDT 24	May 09 12:46:30 PM PDT 24	4288982973 ps
T12	/workspace/coverage/default/49.sram_ctrl_max_throughput.335871176	May 09 12:45:09 PM PDT 24	May 09 12:46:00 PM PDT 24	196727616 ps
T13	/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2547852523	May 09 12:40:56 PM PDT 24	May 09 12:51:01 PM PDT 24	13364372863 ps
T6	/workspace/coverage/default/16.sram_ctrl_stress_pipeline.2960604269	May 09 12:41:52 PM PDT 24	May 09 12:47:20 PM PDT 24	6759347931 ps
T17	/workspace/coverage/default/11.sram_ctrl_mem_walk.2077220640	May 09 12:41:29 PM PDT 24	May 09 12:41:36 PM PDT 24	697487342 ps
T30	/workspace/coverage/default/42.sram_ctrl_ram_cfg.843737536	May 09 12:44:27 PM PDT 24	May 09 12:44:31 PM PDT 24	83225988 ps
T20	/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.2489816291	May 09 12:43:38 PM PDT 24	May 09 12:44:02 PM PDT 24	188946900 ps
T50	/workspace/coverage/default/41.sram_ctrl_stress_pipeline.1748573389	May 09 12:44:15 PM PDT 24	May 09 12:47:18 PM PDT 24	1945148524 ps
T51	/workspace/coverage/default/37.sram_ctrl_executable.1803479238	May 09 12:43:50 PM PDT 24	May 09 12:45:45 PM PDT 24	971628505 ps
T18	/workspace/coverage/default/19.sram_ctrl_mem_walk.326784745	May 09 12:42:10 PM PDT 24	May 09 12:42:17 PM PDT 24	677712215 ps
T19	/workspace/coverage/default/24.sram_ctrl_mem_walk.587825933	May 09 12:42:42 PM PDT 24	May 09 12:42:55 PM PDT 24	659848328 ps
T8	/workspace/coverage/default/11.sram_ctrl_lc_escalation.3040345469	May 09 12:41:35 PM PDT 24	May 09 12:41:42 PM PDT 24	342870722 ps
T14	/workspace/coverage/default/1.sram_ctrl_regwen.2357028415	May 09 12:40:54 PM PDT 24	May 09 12:51:42 PM PDT 24	42777554751 ps
T64	/workspace/coverage/default/9.sram_ctrl_mem_partial_access.3708667859	May 09 12:41:30 PM PDT 24	May 09 12:41:38 PM PDT 24	64570493 ps
T149	/workspace/coverage/default/49.sram_ctrl_mem_walk.2145898486	May 09 02:42:20 PM PDT 24	May 09 02:42:28 PM PDT 24	2046322906 ps
T27	/workspace/coverage/default/6.sram_ctrl_regwen.657892728	May 09 12:41:12 PM PDT 24	May 09 01:05:21 PM PDT 24	2952487546 ps
T94	/workspace/coverage/default/7.sram_ctrl_bijection.2306238907	May 09 12:41:06 PM PDT 24	May 09 12:41:32 PM PDT 24	2444695239 ps
T65	/workspace/coverage/default/0.sram_ctrl_stress_pipeline.846725477	May 09 12:40:56 PM PDT 24	May 09 12:46:24 PM PDT 24	18385030489 ps
T15	/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3903684639	May 09 12:42:46 PM PDT 24	May 09 12:44:00 PM PDT 24	6126187902 ps
T16	/workspace/coverage/default/38.sram_ctrl_stress_all.2387940516	May 09 12:43:56 PM PDT 24	May 09 01:11:18 PM PDT 24	106295519759 ps
T9	/workspace/coverage/default/20.sram_ctrl_stress_all.1206058673	May 09 12:42:11 PM PDT 24	May 09 12:44:07 PM PDT 24	1496882643 ps
T127	/workspace/coverage/default/3.sram_ctrl_executable.218430205	May 09 12:41:05 PM PDT 24	May 09 12:50:07 PM PDT 24	9298478864 ps
T144	/workspace/coverage/default/9.sram_ctrl_partial_access.2993455148	May 09 12:41:19 PM PDT 24	May 09 12:42:17 PM PDT 24	1912951708 ps
T145	/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.256228347	May 09 12:41:39 PM PDT 24	May 09 12:43:55 PM PDT 24	713937580 ps
T150	/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.2519334988	May 09 12:40:57 PM PDT 24	May 09 12:41:24 PM PDT 24	89720675 ps
T143	/workspace/coverage/default/42.sram_ctrl_bijection.432797637	May 09 12:44:15 PM PDT 24	May 09 12:44:46 PM PDT 24	2772411867 ps
T148	/workspace/coverage/default/7.sram_ctrl_max_throughput.63219503	May 09 12:41:11 PM PDT 24	May 09 12:41:21 PM PDT 24	119544176 ps
T24	/workspace/coverage/default/35.sram_ctrl_alert_test.964966800	May 09 12:43:41 PM PDT 24	May 09 12:43:43 PM PDT 24	49151213 ps
T151	/workspace/coverage/default/45.sram_ctrl_partial_access.2650524752	May 09 12:44:36 PM PDT 24	May 09 12:44:46 PM PDT 24	928833027 ps
T90	/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.582084183	May 09 12:41:09 PM PDT 24	May 09 12:46:56 PM PDT 24	19569445226 ps
T140	/workspace/coverage/default/26.sram_ctrl_multiple_keys.2231662433	May 09 12:42:45 PM PDT 24	May 09 12:59:29 PM PDT 24	50946280180 ps
T25	/workspace/coverage/default/16.sram_ctrl_alert_test.1419161579	May 09 12:42:05 PM PDT 24	May 09 12:42:09 PM PDT 24	14775327 ps
T138	/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3832046245	May 09 12:44:08 PM PDT 24	May 09 12:45:03 PM PDT 24	516527682 ps
T152	/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1905656991	May 09 12:42:03 PM PDT 24	May 09 12:43:15 PM PDT 24	136262266 ps
T21	/workspace/coverage/default/3.sram_ctrl_sec_cm.1859580567	May 09 12:41:06 PM PDT 24	May 09 12:41:14 PM PDT 24	4546465748 ps
T35	/workspace/coverage/default/20.sram_ctrl_access_during_key_req.3844259739	May 09 12:42:14 PM PDT 24	May 09 12:52:07 PM PDT 24	33571215139 ps
T36	/workspace/coverage/default/0.sram_ctrl_multiple_keys.4000283995	May 09 12:40:57 PM PDT 24	May 09 12:44:02 PM PDT 24	1314883698 ps
T37	/workspace/coverage/default/0.sram_ctrl_mem_walk.2382229674	May 09 12:40:55 PM PDT 24	May 09 12:41:06 PM PDT 24	450374829 ps
T29	/workspace/coverage/default/7.sram_ctrl_stress_all.2047174322	May 09 12:41:31 PM PDT 24	May 09 12:48:56 PM PDT 24	9414918982 ps
T26	/workspace/coverage/default/31.sram_ctrl_alert_test.723344677	May 09 12:43:18 PM PDT 24	May 09 12:43:20 PM PDT 24	18244420 ps
T38	/workspace/coverage/default/2.sram_ctrl_stress_pipeline.374489600	May 09 12:40:56 PM PDT 24	May 09 12:44:20 PM PDT 24	9702107577 ps
T39	/workspace/coverage/default/37.sram_ctrl_stress_pipeline.1268956058	May 09 12:43:45 PM PDT 24	May 09 12:46:21 PM PDT 24	6755705973 ps
T40	/workspace/coverage/default/41.sram_ctrl_alert_test.206211713	May 09 12:44:20 PM PDT 24	May 09 12:44:23 PM PDT 24	32603290 ps
T41	/workspace/coverage/default/49.sram_ctrl_partial_access.2204883186	May 09 12:45:13 PM PDT 24	May 09 12:45:30 PM PDT 24	1256623354 ps
T52	/workspace/coverage/default/4.sram_ctrl_regwen.1511852604	May 09 12:41:03 PM PDT 24	May 09 01:01:06 PM PDT 24	3721651420 ps
T42	/workspace/coverage/default/43.sram_ctrl_executable.4097437747	May 09 12:44:25 PM PDT 24	May 09 12:54:21 PM PDT 24	16462379968 ps
T139	/workspace/coverage/default/11.sram_ctrl_bijection.3467203825	May 09 12:41:29 PM PDT 24	May 09 12:42:16 PM PDT 24	3973285796 ps
T91	/workspace/coverage/default/33.sram_ctrl_stress_pipeline.2883303625	May 09 12:43:21 PM PDT 24	May 09 12:45:45 PM PDT 24	17598856615 ps
T153	/workspace/coverage/default/47.sram_ctrl_max_throughput.1017207228	May 09 12:44:49 PM PDT 24	May 09 12:46:13 PM PDT 24	483884909 ps
T70	/workspace/coverage/default/36.sram_ctrl_mem_partial_access.2063451530	May 09 12:43:39 PM PDT 24	May 09 12:43:45 PM PDT 24	684365441 ps
T53	/workspace/coverage/default/5.sram_ctrl_lc_escalation.2849351445	May 09 12:41:13 PM PDT 24	May 09 12:41:20 PM PDT 24	540602743 ps
T154	/workspace/coverage/default/37.sram_ctrl_max_throughput.1593204777	May 09 12:43:47 PM PDT 24	May 09 12:45:15 PM PDT 24	262308521 ps
T133	/workspace/coverage/default/41.sram_ctrl_multiple_keys.1022913686	May 09 12:44:15 PM PDT 24	May 09 12:49:17 PM PDT 24	13643330586 ps
T115	/workspace/coverage/default/19.sram_ctrl_lc_escalation.3812168888	May 09 12:42:11 PM PDT 24	May 09 12:42:19 PM PDT 24	2266969562 ps
T28	/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1570335509	May 09 12:42:30 PM PDT 24	May 09 12:51:34 PM PDT 24	27867963666 ps
T142	/workspace/coverage/default/6.sram_ctrl_bijection.1669270185	May 09 12:41:13 PM PDT 24	May 09 12:42:16 PM PDT 24	984579809 ps
T155	/workspace/coverage/default/21.sram_ctrl_mem_walk.3465150133	May 09 12:42:26 PM PDT 24	May 09 12:42:34 PM PDT 24	542281459 ps
T156	/workspace/coverage/default/6.sram_ctrl_partial_access.687474080	May 09 12:41:10 PM PDT 24	May 09 12:41:27 PM PDT 24	1066268781 ps
T134	/workspace/coverage/default/42.sram_ctrl_multiple_keys.2928755007	May 09 12:44:17 PM PDT 24	May 09 12:55:33 PM PDT 24	22023108090 ps
T128	/workspace/coverage/default/15.sram_ctrl_regwen.1166729498	May 09 12:41:52 PM PDT 24	May 09 12:54:52 PM PDT 24	41069504030 ps
T157	/workspace/coverage/default/43.sram_ctrl_bijection.97990610	May 09 12:44:27 PM PDT 24	May 09 12:45:13 PM PDT 24	702402031 ps
T31	/workspace/coverage/default/40.sram_ctrl_ram_cfg.3058307720	May 09 12:44:08 PM PDT 24	May 09 12:44:10 PM PDT 24	45159998 ps
T126	/workspace/coverage/default/13.sram_ctrl_stress_all.3000775779	May 09 12:41:41 PM PDT 24	May 09 02:32:59 PM PDT 24	276774771027 ps
T147	/workspace/coverage/default/13.sram_ctrl_lc_escalation.2881201682	May 09 12:41:44 PM PDT 24	May 09 12:41:52 PM PDT 24	382202797 ps
T146	/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.4207937952	May 09 12:42:17 PM PDT 24	May 09 12:48:39 PM PDT 24	16840511567 ps
T71	/workspace/coverage/default/18.sram_ctrl_access_during_key_req.400706069	May 09 12:42:06 PM PDT 24	May 09 12:45:46 PM PDT 24	1053572932 ps
T116	/workspace/coverage/default/6.sram_ctrl_lc_escalation.2097887309	May 09 12:41:10 PM PDT 24	May 09 12:41:24 PM PDT 24	4214924948 ps
T141	/workspace/coverage/default/36.sram_ctrl_lc_escalation.2862977117	May 09 12:43:40 PM PDT 24	May 09 12:43:49 PM PDT 24	528528986 ps
T43	/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2601765328	May 09 12:41:12 PM PDT 24	May 09 12:50:24 PM PDT 24	3107851323 ps
T72	/workspace/coverage/default/39.sram_ctrl_access_during_key_req.910232905	May 09 12:44:02 PM PDT 24	May 09 12:57:21 PM PDT 24	7512975030 ps
T158	/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1983163340	May 09 12:44:28 PM PDT 24	May 09 12:49:42 PM PDT 24	4526645849 ps
T159	/workspace/coverage/default/44.sram_ctrl_alert_test.2467800354	May 09 12:44:37 PM PDT 24	May 09 12:44:39 PM PDT 24	14603543 ps
T32	/workspace/coverage/default/8.sram_ctrl_ram_cfg.3323567795	May 09 12:41:21 PM PDT 24	May 09 12:41:24 PM PDT 24	44949710 ps
T132	/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1894435581	May 09 12:43:04 PM PDT 24	May 09 12:46:17 PM PDT 24	72132826953 ps
T160	/workspace/coverage/default/27.sram_ctrl_smoke.1405491638	May 09 12:42:53 PM PDT 24	May 09 12:43:07 PM PDT 24	565484421 ps
T129	/workspace/coverage/default/46.sram_ctrl_regwen.1268233234	May 09 12:44:48 PM PDT 24	May 09 12:51:18 PM PDT 24	11031035754 ps
T161	/workspace/coverage/default/44.sram_ctrl_partial_access.3935965481	May 09 12:44:27 PM PDT 24	May 09 12:44:32 PM PDT 24	185780605 ps
T162	/workspace/coverage/default/10.sram_ctrl_regwen.4112112665	May 09 12:41:29 PM PDT 24	May 09 12:44:23 PM PDT 24	5438359870 ps
T163	/workspace/coverage/default/32.sram_ctrl_alert_test.33650391	May 09 12:43:20 PM PDT 24	May 09 12:43:23 PM PDT 24	57629695 ps
T164	/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.2087275596	May 09 12:42:04 PM PDT 24	May 09 12:45:23 PM PDT 24	38815922475 ps
T73	/workspace/coverage/default/22.sram_ctrl_mem_partial_access.3980282873	May 09 12:42:29 PM PDT 24	May 09 12:42:39 PM PDT 24	446742846 ps
T44	/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.117666677	May 09 12:44:28 PM PDT 24	May 09 12:51:27 PM PDT 24	767083869 ps
T130	/workspace/coverage/default/2.sram_ctrl_executable.1657057889	May 09 12:40:56 PM PDT 24	May 09 01:10:55 PM PDT 24	135809511176 ps
T165	/workspace/coverage/default/35.sram_ctrl_mem_walk.1570913463	May 09 12:43:43 PM PDT 24	May 09 12:43:51 PM PDT 24	719043063 ps
T166	/workspace/coverage/default/35.sram_ctrl_max_throughput.235557622	May 09 12:43:28 PM PDT 24	May 09 12:43:46 PM PDT 24	714280644 ps
T45	/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1216472895	May 09 12:45:12 PM PDT 24	May 09 12:45:56 PM PDT 24	6272392151 ps
T167	/workspace/coverage/default/10.sram_ctrl_ram_cfg.1524002905	May 09 12:41:33 PM PDT 24	May 09 12:41:37 PM PDT 24	87958275 ps
T131	/workspace/coverage/default/16.sram_ctrl_stress_all.86535551	May 09 12:42:00 PM PDT 24	May 09 01:37:45 PM PDT 24	55494236762 ps
T74	/workspace/coverage/default/7.sram_ctrl_access_during_key_req.733821391	May 09 12:41:15 PM PDT 24	May 09 01:02:50 PM PDT 24	9704564127 ps
T168	/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.3360164440	May 09 12:43:57 PM PDT 24	May 09 12:47:00 PM PDT 24	7583419360 ps
T169	/workspace/coverage/default/2.sram_ctrl_mem_walk.1452968450	May 09 12:41:00 PM PDT 24	May 09 12:41:09 PM PDT 24	354881953 ps
T137	/workspace/coverage/default/46.sram_ctrl_partial_access.3524931290	May 09 12:44:49 PM PDT 24	May 09 12:45:06 PM PDT 24	536572000 ps
T170	/workspace/coverage/default/40.sram_ctrl_mem_walk.180026506	May 09 12:44:11 PM PDT 24	May 09 12:44:17 PM PDT 24	145185140 ps
T171	/workspace/coverage/default/41.sram_ctrl_partial_access.1318673414	May 09 12:44:15 PM PDT 24	May 09 12:44:30 PM PDT 24	293442851 ps
T172	/workspace/coverage/default/45.sram_ctrl_smoke.3495550736	May 09 12:44:36 PM PDT 24	May 09 12:44:51 PM PDT 24	3204588993 ps
T75	/workspace/coverage/default/15.sram_ctrl_mem_partial_access.808299193	May 09 12:41:50 PM PDT 24	May 09 12:41:57 PM PDT 24	93002541 ps
T135	/workspace/coverage/default/39.sram_ctrl_multiple_keys.613546159	May 09 12:43:59 PM PDT 24	May 09 01:01:27 PM PDT 24	17063719252 ps
T173	/workspace/coverage/default/44.sram_ctrl_mem_partial_access.1465966959	May 09 12:44:38 PM PDT 24	May 09 12:44:42 PM PDT 24	195861911 ps
T174	/workspace/coverage/default/28.sram_ctrl_stress_pipeline.3242424367	May 09 12:42:55 PM PDT 24	May 09 12:46:39 PM PDT 24	17612411161 ps
T175	/workspace/coverage/default/43.sram_ctrl_stress_all.3395931576	May 09 12:44:26 PM PDT 24	May 09 01:23:29 PM PDT 24	37207729036 ps
T176	/workspace/coverage/default/32.sram_ctrl_smoke.712510464	May 09 12:43:19 PM PDT 24	May 09 12:43:36 PM PDT 24	1327897084 ps
T177	/workspace/coverage/default/43.sram_ctrl_lc_escalation.4134044376	May 09 12:44:25 PM PDT 24	May 09 12:44:34 PM PDT 24	5412297836 ps
T178	/workspace/coverage/default/19.sram_ctrl_access_during_key_req.3561777899	May 09 12:42:10 PM PDT 24	May 09 12:59:18 PM PDT 24	3334373132 ps
T179	/workspace/coverage/default/25.sram_ctrl_ram_cfg.2772355055	May 09 12:42:43 PM PDT 24	May 09 12:42:46 PM PDT 24	50654744 ps
T180	/workspace/coverage/default/27.sram_ctrl_access_during_key_req.3640602657	May 09 12:42:52 PM PDT 24	May 09 12:51:58 PM PDT 24	33630153358 ps
T136	/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.4218892680	May 09 12:43:23 PM PDT 24	May 09 12:52:15 PM PDT 24	95288948996 ps
T181	/workspace/coverage/default/19.sram_ctrl_smoke.782706651	May 09 12:42:06 PM PDT 24	May 09 12:42:18 PM PDT 24	2525422915 ps
T182	/workspace/coverage/default/16.sram_ctrl_lc_escalation.1013222337	May 09 12:42:01 PM PDT 24	May 09 12:42:12 PM PDT 24	7854659513 ps
T183	/workspace/coverage/default/34.sram_ctrl_bijection.3971383441	May 09 12:43:32 PM PDT 24	May 09 12:44:07 PM PDT 24	5851253660 ps
T184	/workspace/coverage/default/16.sram_ctrl_smoke.43520577	May 09 12:41:51 PM PDT 24	May 09 12:42:04 PM PDT 24	307450839 ps
T185	/workspace/coverage/default/12.sram_ctrl_access_during_key_req.2604059477	May 09 12:41:39 PM PDT 24	May 09 01:00:21 PM PDT 24	10595002746 ps
T186	/workspace/coverage/default/4.sram_ctrl_mem_walk.1825297017	May 09 12:41:09 PM PDT 24	May 09 12:41:20 PM PDT 24	1040142833 ps
T187	/workspace/coverage/default/32.sram_ctrl_executable.2905177593	May 09 12:43:21 PM PDT 24	May 09 01:03:23 PM PDT 24	91661168677 ps
T188	/workspace/coverage/default/38.sram_ctrl_lc_escalation.1941720193	May 09 12:43:51 PM PDT 24	May 09 12:44:01 PM PDT 24	3861021158 ps
T189	/workspace/coverage/default/36.sram_ctrl_stress_pipeline.260109737	May 09 12:43:38 PM PDT 24	May 09 12:47:52 PM PDT 24	2720518719 ps
T190	/workspace/coverage/default/22.sram_ctrl_bijection.2856207411	May 09 12:42:21 PM PDT 24	May 09 12:43:43 PM PDT 24	18066582372 ps
T191	/workspace/coverage/default/43.sram_ctrl_alert_test.4147217907	May 09 12:44:27 PM PDT 24	May 09 12:44:31 PM PDT 24	70719276 ps
T192	/workspace/coverage/default/1.sram_ctrl_ram_cfg.923817236	May 09 12:40:55 PM PDT 24	May 09 12:40:59 PM PDT 24	47522209 ps
T193	/workspace/coverage/default/29.sram_ctrl_bijection.3470368315	May 09 12:42:59 PM PDT 24	May 09 12:44:19 PM PDT 24	14479342527 ps
T194	/workspace/coverage/default/47.sram_ctrl_regwen.2508700463	May 09 12:44:59 PM PDT 24	May 09 01:07:00 PM PDT 24	19183826431 ps
T117	/workspace/coverage/default/3.sram_ctrl_stress_all.3470604047	May 09 12:41:12 PM PDT 24	May 09 12:47:22 PM PDT 24	29867865830 ps
T195	/workspace/coverage/default/14.sram_ctrl_mem_walk.3961707862	May 09 12:41:51 PM PDT 24	May 09 12:42:01 PM PDT 24	664207021 ps
T196	/workspace/coverage/default/31.sram_ctrl_stress_all.3654831050	May 09 12:43:17 PM PDT 24	May 09 01:46:12 PM PDT 24	162946150962 ps
T197	/workspace/coverage/default/27.sram_ctrl_regwen.4046660495	May 09 12:42:55 PM PDT 24	May 09 12:56:48 PM PDT 24	1721092032 ps
T198	/workspace/coverage/default/41.sram_ctrl_access_during_key_req.3412102787	May 09 12:44:16 PM PDT 24	May 09 12:55:27 PM PDT 24	2729272161 ps
T199	/workspace/coverage/default/48.sram_ctrl_lc_escalation.1602406490	May 09 12:45:01 PM PDT 24	May 09 12:45:07 PM PDT 24	974019837 ps
T200	/workspace/coverage/default/21.sram_ctrl_max_throughput.120603718	May 09 12:42:21 PM PDT 24	May 09 12:44:28 PM PDT 24	270571565 ps
T201	/workspace/coverage/default/21.sram_ctrl_multiple_keys.2831670322	May 09 12:42:10 PM PDT 24	May 09 01:00:19 PM PDT 24	22512306150 ps
T202	/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3625342990	May 09 12:41:31 PM PDT 24	May 09 12:45:59 PM PDT 24	31735823975 ps
T203	/workspace/coverage/default/13.sram_ctrl_alert_test.540428184	May 09 12:41:39 PM PDT 24	May 09 12:41:44 PM PDT 24	97091838 ps
T204	/workspace/coverage/default/43.sram_ctrl_partial_access.225539054	May 09 12:44:26 PM PDT 24	May 09 12:44:49 PM PDT 24	128943837 ps
T205	/workspace/coverage/default/17.sram_ctrl_lc_escalation.1884341373	May 09 12:42:04 PM PDT 24	May 09 12:42:12 PM PDT 24	565128214 ps
T206	/workspace/coverage/default/10.sram_ctrl_max_throughput.153861166	May 09 12:41:30 PM PDT 24	May 09 12:43:08 PM PDT 24	130419513 ps
T207	/workspace/coverage/default/15.sram_ctrl_multiple_keys.3872496780	May 09 12:41:50 PM PDT 24	May 09 12:58:41 PM PDT 24	69322697987 ps
T208	/workspace/coverage/default/23.sram_ctrl_smoke.1883269524	May 09 12:42:30 PM PDT 24	May 09 12:42:41 PM PDT 24	280035434 ps
T46	/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1709501703	May 09 12:44:36 PM PDT 24	May 09 12:44:45 PM PDT 24	898196655 ps
T106	/workspace/coverage/default/24.sram_ctrl_regwen.3146143562	May 09 12:42:43 PM PDT 24	May 09 12:49:35 PM PDT 24	20161351412 ps
T107	/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3061102105	May 09 12:41:08 PM PDT 24	May 09 12:41:13 PM PDT 24	357650680 ps
T108	/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.2376787383	May 09 12:43:30 PM PDT 24	May 09 12:47:34 PM PDT 24	13692940212 ps
T109	/workspace/coverage/default/39.sram_ctrl_regwen.1217964976	May 09 12:43:58 PM PDT 24	May 09 01:01:52 PM PDT 24	17481171240 ps
T110	/workspace/coverage/default/44.sram_ctrl_mem_walk.2258097037	May 09 12:44:35 PM PDT 24	May 09 12:44:41 PM PDT 24	147237371 ps
T111	/workspace/coverage/default/1.sram_ctrl_alert_test.645840807	May 09 12:40:57 PM PDT 24	May 09 12:41:03 PM PDT 24	14198294 ps
T112	/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2319624474	May 09 12:43:09 PM PDT 24	May 09 12:44:33 PM PDT 24	547806955 ps
T113	/workspace/coverage/default/12.sram_ctrl_multiple_keys.3894784636	May 09 12:41:33 PM PDT 24	May 09 12:53:30 PM PDT 24	7767115439 ps
T114	/workspace/coverage/default/25.sram_ctrl_bijection.2364628279	May 09 12:42:44 PM PDT 24	May 09 12:43:42 PM PDT 24	2686057169 ps
T209	/workspace/coverage/default/19.sram_ctrl_partial_access.3346293827	May 09 12:42:05 PM PDT 24	May 09 12:42:23 PM PDT 24	3188633459 ps
T210	/workspace/coverage/default/7.sram_ctrl_multiple_keys.1115355654	May 09 12:41:09 PM PDT 24	May 09 12:43:23 PM PDT 24	7163957038 ps
T211	/workspace/coverage/default/8.sram_ctrl_mem_walk.4145167319	May 09 12:41:26 PM PDT 24	May 09 12:41:34 PM PDT 24	2046225523 ps
T212	/workspace/coverage/default/28.sram_ctrl_access_during_key_req.467774621	May 09 12:42:54 PM PDT 24	May 09 12:52:00 PM PDT 24	11340880126 ps
T213	/workspace/coverage/default/11.sram_ctrl_max_throughput.3826697223	May 09 12:41:30 PM PDT 24	May 09 12:42:29 PM PDT 24	255480887 ps
T214	/workspace/coverage/default/5.sram_ctrl_stress_all.579758349	May 09 12:41:07 PM PDT 24	May 09 01:55:42 PM PDT 24	75289528254 ps
T47	/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2080008510	May 09 12:41:33 PM PDT 24	May 09 12:44:22 PM PDT 24	2531211389 ps
T215	/workspace/coverage/default/21.sram_ctrl_stress_all.1268836422	May 09 12:42:20 PM PDT 24	May 09 12:46:51 PM PDT 24	3104817302 ps
T216	/workspace/coverage/default/49.sram_ctrl_executable.1082521221	May 09 02:31:14 PM PDT 24	May 09 02:42:30 PM PDT 24	36733669123 ps
T217	/workspace/coverage/default/13.sram_ctrl_mem_partial_access.2048453439	May 09 12:41:39 PM PDT 24	May 09 12:41:47 PM PDT 24	473115989 ps
T218	/workspace/coverage/default/35.sram_ctrl_smoke.950331673	May 09 12:43:30 PM PDT 24	May 09 12:43:43 PM PDT 24	680364613 ps
T219	/workspace/coverage/default/22.sram_ctrl_mem_walk.3444010297	May 09 12:42:20 PM PDT 24	May 09 12:42:33 PM PDT 24	1336338327 ps
T220	/workspace/coverage/default/29.sram_ctrl_regwen.1940654228	May 09 12:43:00 PM PDT 24	May 09 12:46:32 PM PDT 24	14993902986 ps
T221	/workspace/coverage/default/45.sram_ctrl_mem_walk.4202516140	May 09 12:44:35 PM PDT 24	May 09 12:44:42 PM PDT 24	938604149 ps
T222	/workspace/coverage/default/17.sram_ctrl_mem_walk.2565081031	May 09 12:42:03 PM PDT 24	May 09 12:42:12 PM PDT 24	297765392 ps
T48	/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3767114698	May 09 12:42:13 PM PDT 24	May 09 12:55:19 PM PDT 24	1869785764 ps
T223	/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.635136639	May 09 12:44:17 PM PDT 24	May 09 12:46:07 PM PDT 24	1213310615 ps
T224	/workspace/coverage/default/23.sram_ctrl_regwen.1255813846	May 09 12:42:29 PM PDT 24	May 09 12:57:28 PM PDT 24	91106602994 ps
T225	/workspace/coverage/default/30.sram_ctrl_lc_escalation.4049158312	May 09 12:43:12 PM PDT 24	May 09 12:43:16 PM PDT 24	133324476 ps
T226	/workspace/coverage/default/42.sram_ctrl_mem_partial_access.3797385586	May 09 12:44:25 PM PDT 24	May 09 12:44:30 PM PDT 24	354809774 ps
T227	/workspace/coverage/default/46.sram_ctrl_multiple_keys.1780301331	May 09 12:44:47 PM PDT 24	May 09 12:57:53 PM PDT 24	11649472132 ps
T228	/workspace/coverage/default/12.sram_ctrl_max_throughput.958690640	May 09 12:41:38 PM PDT 24	May 09 12:43:02 PM PDT 24	541442146 ps
T229	/workspace/coverage/default/16.sram_ctrl_access_during_key_req.1955343914	May 09 12:42:02 PM PDT 24	May 09 12:57:29 PM PDT 24	3593088601 ps
T230	/workspace/coverage/default/5.sram_ctrl_regwen.1225825571	May 09 12:41:12 PM PDT 24	May 09 01:01:35 PM PDT 24	49315227450 ps
T231	/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1093100699	May 09 12:41:08 PM PDT 24	May 09 12:41:21 PM PDT 24	308893307 ps
T232	/workspace/coverage/default/12.sram_ctrl_lc_escalation.4216596998	May 09 12:41:39 PM PDT 24	May 09 12:41:49 PM PDT 24	355465564 ps
T233	/workspace/coverage/default/8.sram_ctrl_executable.3401261273	May 09 12:41:18 PM PDT 24	May 09 12:42:32 PM PDT 24	1984290564 ps
T234	/workspace/coverage/default/10.sram_ctrl_mem_walk.3317050402	May 09 12:41:33 PM PDT 24	May 09 12:41:42 PM PDT 24	343283580 ps
T235	/workspace/coverage/default/31.sram_ctrl_stress_pipeline.350911774	May 09 12:43:09 PM PDT 24	May 09 12:46:53 PM PDT 24	13075833556 ps
T236	/workspace/coverage/default/6.sram_ctrl_max_throughput.2825906970	May 09 12:41:10 PM PDT 24	May 09 12:42:42 PM PDT 24	119632636 ps
T237	/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2687894858	May 09 12:44:58 PM PDT 24	May 09 12:45:04 PM PDT 24	69216864 ps
T49	/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.816206056	May 09 12:41:30 PM PDT 24	May 09 12:42:55 PM PDT 24	5339324002 ps
T238	/workspace/coverage/default/43.sram_ctrl_ram_cfg.2100527728	May 09 12:44:24 PM PDT 24	May 09 12:44:26 PM PDT 24	83832806 ps
T239	/workspace/coverage/default/35.sram_ctrl_access_during_key_req.3302363858	May 09 12:43:40 PM PDT 24	May 09 12:59:07 PM PDT 24	9334232784 ps
T240	/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3595115603	May 09 12:44:47 PM PDT 24	May 09 12:46:36 PM PDT 24	270620943 ps
T241	/workspace/coverage/default/43.sram_ctrl_smoke.3470652369	May 09 12:44:28 PM PDT 24	May 09 12:44:41 PM PDT 24	934678027 ps
T242	/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2440640462	May 09 12:41:50 PM PDT 24	May 09 12:47:56 PM PDT 24	31853403847 ps
T243	/workspace/coverage/default/42.sram_ctrl_executable.55527395	May 09 12:44:16 PM PDT 24	May 09 12:50:06 PM PDT 24	828845633 ps
T244	/workspace/coverage/default/14.sram_ctrl_alert_test.657215537	May 09 12:41:52 PM PDT 24	May 09 12:41:57 PM PDT 24	32480765 ps
T245	/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1002989914	May 09 12:43:09 PM PDT 24	May 09 12:49:18 PM PDT 24	3609547087 ps
T98	/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3764068813	May 09 12:44:26 PM PDT 24	May 09 12:44:56 PM PDT 24	5342809105 ps
T246	/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.2069955440	May 09 12:43:56 PM PDT 24	May 09 12:45:04 PM PDT 24	1026429047 ps
T247	/workspace/coverage/default/18.sram_ctrl_max_throughput.2367395400	May 09 12:42:04 PM PDT 24	May 09 12:42:28 PM PDT 24	149004703 ps
T248	/workspace/coverage/default/12.sram_ctrl_executable.1902565855	May 09 12:41:39 PM PDT 24	May 09 12:49:19 PM PDT 24	7653104949 ps
T249	/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.2628049086	May 09 12:43:19 PM PDT 24	May 09 12:43:34 PM PDT 24	74519571 ps
T250	/workspace/coverage/default/29.sram_ctrl_multiple_keys.2577484047	May 09 12:43:03 PM PDT 24	May 09 12:54:15 PM PDT 24	21920816430 ps
T251	/workspace/coverage/default/42.sram_ctrl_access_during_key_req.1242463882	May 09 12:44:17 PM PDT 24	May 09 12:59:09 PM PDT 24	14859416350 ps
T252	/workspace/coverage/default/40.sram_ctrl_executable.2786991932	May 09 12:44:09 PM PDT 24	May 09 01:02:39 PM PDT 24	54121767642 ps
T253	/workspace/coverage/default/38.sram_ctrl_stress_pipeline.1234110427	May 09 12:43:51 PM PDT 24	May 09 12:47:29 PM PDT 24	2406722786 ps
T254	/workspace/coverage/default/40.sram_ctrl_partial_access.2664759831	May 09 12:44:07 PM PDT 24	May 09 12:46:00 PM PDT 24	1621427661 ps
T255	/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.71103380	May 09 12:44:07 PM PDT 24	May 09 12:46:26 PM PDT 24	1405032403 ps
T256	/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.524659450	May 09 12:43:19 PM PDT 24	May 09 12:47:35 PM PDT 24	13036074256 ps
T257	/workspace/coverage/default/49.sram_ctrl_bijection.456543758	May 09 12:45:07 PM PDT 24	May 09 12:45:53 PM PDT 24	6348006042 ps
T258	/workspace/coverage/default/0.sram_ctrl_regwen.2215921099	May 09 12:40:55 PM PDT 24	May 09 12:53:51 PM PDT 24	12787510608 ps
T22	/workspace/coverage/default/2.sram_ctrl_sec_cm.379503642	May 09 12:40:59 PM PDT 24	May 09 12:41:06 PM PDT 24	334376083 ps
T259	/workspace/coverage/default/33.sram_ctrl_smoke.1766131412	May 09 12:43:21 PM PDT 24	May 09 12:43:31 PM PDT 24	410504823 ps
T260	/workspace/coverage/default/17.sram_ctrl_regwen.3723125574	May 09 12:42:03 PM PDT 24	May 09 12:50:09 PM PDT 24	49164572410 ps
T261	/workspace/coverage/default/25.sram_ctrl_multiple_keys.1317361035	May 09 12:42:44 PM PDT 24	May 09 01:00:29 PM PDT 24	11489185323 ps
T262	/workspace/coverage/default/11.sram_ctrl_partial_access.2549413265	May 09 12:41:31 PM PDT 24	May 09 12:41:56 PM PDT 24	2787392511 ps
T263	/workspace/coverage/default/46.sram_ctrl_max_throughput.4001676494	May 09 12:44:45 PM PDT 24	May 09 12:45:55 PM PDT 24	1284471511 ps
T264	/workspace/coverage/default/44.sram_ctrl_stress_pipeline.3100765672	May 09 12:44:27 PM PDT 24	May 09 12:48:45 PM PDT 24	17080416783 ps
T265	/workspace/coverage/default/19.sram_ctrl_max_throughput.2011320070	May 09 12:42:03 PM PDT 24	May 09 12:43:00 PM PDT 24	110202096 ps
T266	/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.469037149	May 09 12:42:52 PM PDT 24	May 09 12:45:54 PM PDT 24	11443675107 ps
T99	/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1176404155	May 09 12:41:09 PM PDT 24	May 09 12:41:29 PM PDT 24	668559182 ps
T267	/workspace/coverage/default/47.sram_ctrl_partial_access.1087124566	May 09 12:44:50 PM PDT 24	May 09 12:45:05 PM PDT 24	272520557 ps
T268	/workspace/coverage/default/12.sram_ctrl_bijection.2469082588	May 09 12:41:32 PM PDT 24	May 09 12:42:06 PM PDT 24	7857571805 ps
T269	/workspace/coverage/default/43.sram_ctrl_mem_walk.988103524	May 09 12:44:25 PM PDT 24	May 09 12:44:36 PM PDT 24	627145352 ps
T270	/workspace/coverage/default/38.sram_ctrl_multiple_keys.3119602971	May 09 12:43:47 PM PDT 24	May 09 01:00:57 PM PDT 24	12107582591 ps
T271	/workspace/coverage/default/20.sram_ctrl_executable.1041595621	May 09 12:42:20 PM PDT 24	May 09 12:54:07 PM PDT 24	2288904373 ps
T272	/workspace/coverage/default/49.sram_ctrl_lc_escalation.2282373971	May 09 03:56:25 PM PDT 24	May 09 03:56:31 PM PDT 24	442150781 ps
T273	/workspace/coverage/default/18.sram_ctrl_bijection.1974740404	May 09 12:42:02 PM PDT 24	May 09 12:42:29 PM PDT 24	7656184806 ps
T274	/workspace/coverage/default/8.sram_ctrl_max_throughput.2855482132	May 09 12:41:17 PM PDT 24	May 09 12:41:33 PM PDT 24	548894268 ps
T275	/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1393292945	May 09 12:44:16 PM PDT 24	May 09 12:51:21 PM PDT 24	63375141440 ps
T276	/workspace/coverage/default/32.sram_ctrl_access_during_key_req.2718959760	May 09 12:43:19 PM PDT 24	May 09 12:52:32 PM PDT 24	2276035580 ps
T277	/workspace/coverage/default/15.sram_ctrl_bijection.2595167015	May 09 12:41:52 PM PDT 24	May 09 12:42:42 PM PDT 24	6356756114 ps
T278	/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.3368697116	May 09 12:43:45 PM PDT 24	May 09 12:48:06 PM PDT 24	51477535166 ps
T279	/workspace/coverage/default/9.sram_ctrl_alert_test.3600016793	May 09 12:41:30 PM PDT 24	May 09 12:41:34 PM PDT 24	17741672 ps
T280	/workspace/coverage/default/19.sram_ctrl_mem_partial_access.3542082496	May 09 12:42:11 PM PDT 24	May 09 12:42:17 PM PDT 24	247173962 ps
T281	/workspace/coverage/default/5.sram_ctrl_alert_test.1715977776	May 09 12:41:08 PM PDT 24	May 09 12:41:10 PM PDT 24	21119199 ps
T282	/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3457264384	May 09 12:45:08 PM PDT 24	May 09 12:45:41 PM PDT 24	1051804974 ps
T283	/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3574264409	May 09 12:41:32 PM PDT 24	May 09 12:42:40 PM PDT 24	1312495693 ps
T284	/workspace/coverage/default/35.sram_ctrl_stress_pipeline.1908017021	May 09 12:43:27 PM PDT 24	May 09 12:48:02 PM PDT 24	6508123535 ps
T285	/workspace/coverage/default/40.sram_ctrl_lc_escalation.3102705635	May 09 12:44:07 PM PDT 24	May 09 12:44:11 PM PDT 24	956601193 ps
T286	/workspace/coverage/default/8.sram_ctrl_partial_access.3726857463	May 09 12:41:24 PM PDT 24	May 09 12:42:50 PM PDT 24	1288164902 ps
T287	/workspace/coverage/default/36.sram_ctrl_smoke.1083704695	May 09 12:43:40 PM PDT 24	May 09 12:43:58 PM PDT 24	7506733309 ps
T288	/workspace/coverage/default/19.sram_ctrl_executable.3079111601	May 09 12:42:14 PM PDT 24	May 09 12:58:14 PM PDT 24	10964284405 ps
T289	/workspace/coverage/default/47.sram_ctrl_stress_pipeline.1984877684	May 09 12:44:49 PM PDT 24	May 09 12:49:38 PM PDT 24	13407903178 ps
T290	/workspace/coverage/default/4.sram_ctrl_access_during_key_req.3106825508	May 09 12:41:06 PM PDT 24	May 09 01:04:19 PM PDT 24	8470284968 ps
T291	/workspace/coverage/default/44.sram_ctrl_lc_escalation.2355919157	May 09 12:44:25 PM PDT 24	May 09 12:44:28 PM PDT 24	251651702 ps
T292	/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.400659875	May 09 12:42:02 PM PDT 24	May 09 12:42:19 PM PDT 24	222058419 ps
T293	/workspace/coverage/default/31.sram_ctrl_smoke.245749452	May 09 12:43:10 PM PDT 24	May 09 12:43:17 PM PDT 24	370034831 ps
T294	/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.2681809662	May 09 12:44:08 PM PDT 24	May 09 12:46:55 PM PDT 24	6563807669 ps
T295	/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1130790203	May 09 12:40:54 PM PDT 24	May 09 12:45:01 PM PDT 24	23239725118 ps
T296	/workspace/coverage/default/13.sram_ctrl_multiple_keys.2120194592	May 09 12:41:42 PM PDT 24	May 09 12:46:54 PM PDT 24	3394510097 ps
T297	/workspace/coverage/default/2.sram_ctrl_access_during_key_req.94054805	May 09 12:40:55 PM PDT 24	May 09 12:46:25 PM PDT 24	5136338908 ps
T298	/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1892855640	May 09 12:41:15 PM PDT 24	May 09 12:44:03 PM PDT 24	3543576307 ps
T299	/workspace/coverage/default/24.sram_ctrl_alert_test.1615243826	May 09 12:42:44 PM PDT 24	May 09 12:42:47 PM PDT 24	37051216 ps
T300	/workspace/coverage/default/31.sram_ctrl_max_throughput.1218809850	May 09 12:43:12 PM PDT 24	May 09 12:43:17 PM PDT 24	52822273 ps