Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	43342684	1			T1	6142		T2	64591		T3	171015
triple_byte_access	2515715	1			T2	1309		T3	3511		T4	6309
halfword_access	3773208	1			T2	1890		T3	5079		T4	9301
byte_access	5042128	1			T2	2622		T3	6726		T4	12418
zero_access	1267801	1			T2	642		T3	1714		T4	3114

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27920630

1

T1

2048

T2

35662

T3

94073

auto[1]

28020906

1

T1

4094

T2

35392

T3

93972

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21625062	1			T1	2048		T2	32394		T3	85596
auto[0]	triple_byte_access	1255273	1			T2	667		T3	1737		T4	3083
auto[0]	halfword_access	1881941	1			T2	954		T3	2551		T4	4637
auto[0]	byte_access	2520452	1			T2	1292		T3	3359		T4	6126
auto[0]	zero_access	637902	1			T2	355		T3	830		T4	1600
auto[1]	word_access	21717622	1			T1	4094		T2	32197		T3	85419
auto[1]	triple_byte_access	1260442	1			T2	642		T3	1774		T4	3226
auto[1]	halfword_access	1891267	1			T2	936		T3	2528		T4	4664
auto[1]	byte_access	2521676	1			T2	1330		T3	3367		T4	6292
auto[1]	zero_access	629899	1			T2	287		T3	884		T4	1514