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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.08 99.81 96.99 100.00 100.00 98.57 99.70 98.52


Total test records in report: 1024
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T790 /workspace/coverage/default/26.sram_ctrl_lc_escalation.2504274056 May 09 12:42:51 PM PDT 24 May 09 12:42:56 PM PDT 24 658759773 ps
T791 /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3944567036 May 09 12:41:41 PM PDT 24 May 09 12:42:49 PM PDT 24 238141381 ps
T792 /workspace/coverage/default/35.sram_ctrl_executable.3413730205 May 09 12:43:42 PM PDT 24 May 09 01:01:46 PM PDT 24 12301684330 ps
T793 /workspace/coverage/default/4.sram_ctrl_alert_test.2598192406 May 09 12:41:08 PM PDT 24 May 09 12:41:11 PM PDT 24 36138228 ps
T794 /workspace/coverage/default/45.sram_ctrl_max_throughput.2203013961 May 09 12:44:35 PM PDT 24 May 09 12:45:14 PM PDT 24 493370408 ps
T795 /workspace/coverage/default/19.sram_ctrl_stress_pipeline.820670888 May 09 12:42:03 PM PDT 24 May 09 12:45:45 PM PDT 24 32249564910 ps
T796 /workspace/coverage/default/27.sram_ctrl_multiple_keys.2902071875 May 09 12:42:57 PM PDT 24 May 09 12:43:46 PM PDT 24 365989589 ps
T797 /workspace/coverage/default/2.sram_ctrl_max_throughput.3694339502 May 09 12:40:58 PM PDT 24 May 09 12:41:04 PM PDT 24 42883360 ps
T798 /workspace/coverage/default/21.sram_ctrl_partial_access.2470304287 May 09 12:42:13 PM PDT 24 May 09 12:42:30 PM PDT 24 809310015 ps
T799 /workspace/coverage/default/20.sram_ctrl_partial_access.2438635072 May 09 12:42:11 PM PDT 24 May 09 12:42:26 PM PDT 24 530086442 ps
T800 /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3819273026 May 09 12:43:29 PM PDT 24 May 09 12:44:06 PM PDT 24 945953415 ps
T801 /workspace/coverage/default/17.sram_ctrl_partial_access.3953732778 May 09 12:42:01 PM PDT 24 May 09 12:42:21 PM PDT 24 1047319856 ps
T802 /workspace/coverage/default/26.sram_ctrl_ram_cfg.407762108 May 09 12:42:51 PM PDT 24 May 09 12:42:54 PM PDT 24 51229895 ps
T803 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.954452851 May 09 12:42:19 PM PDT 24 May 09 12:44:48 PM PDT 24 3872745752 ps
T804 /workspace/coverage/default/19.sram_ctrl_bijection.3542911745 May 09 12:42:04 PM PDT 24 May 09 12:42:44 PM PDT 24 14099917112 ps
T805 /workspace/coverage/default/28.sram_ctrl_partial_access.3146442004 May 09 12:42:55 PM PDT 24 May 09 12:43:28 PM PDT 24 119055258 ps
T806 /workspace/coverage/default/31.sram_ctrl_executable.2735658147 May 09 12:43:09 PM PDT 24 May 09 12:52:56 PM PDT 24 9684177902 ps
T807 /workspace/coverage/default/48.sram_ctrl_multiple_keys.534363549 May 09 12:44:58 PM PDT 24 May 09 01:03:16 PM PDT 24 95372774405 ps
T808 /workspace/coverage/default/24.sram_ctrl_ram_cfg.1036029870 May 09 12:42:43 PM PDT 24 May 09 12:42:46 PM PDT 24 87855405 ps
T809 /workspace/coverage/default/40.sram_ctrl_mem_partial_access.4189209833 May 09 12:44:08 PM PDT 24 May 09 12:44:14 PM PDT 24 237858142 ps
T810 /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2027438886 May 09 12:42:41 PM PDT 24 May 09 12:44:26 PM PDT 24 1088016326 ps
T811 /workspace/coverage/default/38.sram_ctrl_executable.173458112 May 09 12:43:47 PM PDT 24 May 09 12:44:11 PM PDT 24 403317422 ps
T812 /workspace/coverage/default/45.sram_ctrl_mem_partial_access.528968978 May 09 12:44:35 PM PDT 24 May 09 12:44:39 PM PDT 24 85693727 ps
T813 /workspace/coverage/default/20.sram_ctrl_multiple_keys.1810673610 May 09 12:42:20 PM PDT 24 May 09 01:01:30 PM PDT 24 66170858067 ps
T814 /workspace/coverage/default/37.sram_ctrl_mem_partial_access.3893991030 May 09 12:43:50 PM PDT 24 May 09 12:43:56 PM PDT 24 168025232 ps
T815 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1567071537 May 09 12:42:29 PM PDT 24 May 09 12:48:56 PM PDT 24 65811653878 ps
T816 /workspace/coverage/default/0.sram_ctrl_partial_access.970253419 May 09 12:40:58 PM PDT 24 May 09 12:41:20 PM PDT 24 2001449961 ps
T817 /workspace/coverage/default/14.sram_ctrl_ram_cfg.2099737461 May 09 12:41:52 PM PDT 24 May 09 12:41:57 PM PDT 24 31306808 ps
T818 /workspace/coverage/default/41.sram_ctrl_ram_cfg.2769063853 May 09 12:44:18 PM PDT 24 May 09 12:44:22 PM PDT 24 30771731 ps
T819 /workspace/coverage/default/36.sram_ctrl_multiple_keys.3464941015 May 09 12:43:37 PM PDT 24 May 09 01:16:21 PM PDT 24 7141843857 ps
T820 /workspace/coverage/default/15.sram_ctrl_lc_escalation.454101080 May 09 12:41:51 PM PDT 24 May 09 12:42:07 PM PDT 24 10742584702 ps
T821 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.2979311751 May 09 12:44:00 PM PDT 24 May 09 12:44:05 PM PDT 24 57795844 ps
T822 /workspace/coverage/default/30.sram_ctrl_multiple_keys.3055428544 May 09 12:43:00 PM PDT 24 May 09 12:43:12 PM PDT 24 744024047 ps
T823 /workspace/coverage/default/6.sram_ctrl_ram_cfg.1073465226 May 09 12:41:13 PM PDT 24 May 09 12:41:16 PM PDT 24 77218538 ps
T824 /workspace/coverage/default/26.sram_ctrl_alert_test.3889685922 May 09 12:42:52 PM PDT 24 May 09 12:42:54 PM PDT 24 32920924 ps
T825 /workspace/coverage/default/10.sram_ctrl_executable.3452780647 May 09 12:41:30 PM PDT 24 May 09 12:50:01 PM PDT 24 34159116705 ps
T826 /workspace/coverage/default/33.sram_ctrl_alert_test.3586131167 May 09 12:43:31 PM PDT 24 May 09 12:43:34 PM PDT 24 34057268 ps
T827 /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1625360489 May 09 12:44:18 PM PDT 24 May 09 12:47:00 PM PDT 24 629151312 ps
T828 /workspace/coverage/default/18.sram_ctrl_ram_cfg.1626804058 May 09 12:42:06 PM PDT 24 May 09 12:42:10 PM PDT 24 83795065 ps
T829 /workspace/coverage/default/38.sram_ctrl_partial_access.1895774788 May 09 12:43:47 PM PDT 24 May 09 12:44:05 PM PDT 24 532015329 ps
T34 /workspace/coverage/default/4.sram_ctrl_sec_cm.1524232086 May 09 12:41:04 PM PDT 24 May 09 12:41:08 PM PDT 24 392686012 ps
T830 /workspace/coverage/default/46.sram_ctrl_ram_cfg.2364830431 May 09 12:44:46 PM PDT 24 May 09 12:44:48 PM PDT 24 29654505 ps
T831 /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.2577145109 May 09 12:43:44 PM PDT 24 May 09 12:43:50 PM PDT 24 60023853 ps
T832 /workspace/coverage/default/23.sram_ctrl_executable.1367077988 May 09 12:42:29 PM PDT 24 May 09 12:48:48 PM PDT 24 4466938629 ps
T833 /workspace/coverage/default/37.sram_ctrl_mem_walk.1627584754 May 09 12:43:46 PM PDT 24 May 09 12:43:57 PM PDT 24 873921452 ps
T834 /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2034907713 May 09 12:42:53 PM PDT 24 May 09 12:46:01 PM PDT 24 1485599714 ps
T835 /workspace/coverage/default/46.sram_ctrl_stress_all.3747559610 May 09 12:45:02 PM PDT 24 May 09 01:28:04 PM PDT 24 9385515309 ps
T836 /workspace/coverage/default/25.sram_ctrl_alert_test.1737234021 May 09 12:42:42 PM PDT 24 May 09 12:42:45 PM PDT 24 32491276 ps
T837 /workspace/coverage/default/35.sram_ctrl_multiple_keys.2226600518 May 09 12:43:29 PM PDT 24 May 09 12:45:23 PM PDT 24 19565866969 ps
T838 /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2649038397 May 09 12:41:15 PM PDT 24 May 09 12:41:40 PM PDT 24 91666192 ps
T839 /workspace/coverage/default/8.sram_ctrl_lc_escalation.1275360852 May 09 12:41:19 PM PDT 24 May 09 12:41:23 PM PDT 24 453142774 ps
T840 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.2122859971 May 09 12:44:59 PM PDT 24 May 09 12:45:03 PM PDT 24 42819563 ps
T841 /workspace/coverage/default/18.sram_ctrl_regwen.631591817 May 09 12:42:06 PM PDT 24 May 09 12:48:06 PM PDT 24 3045013884 ps
T842 /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2082197110 May 09 12:42:54 PM PDT 24 May 09 12:47:21 PM PDT 24 921524217 ps
T843 /workspace/coverage/default/25.sram_ctrl_regwen.3088474998 May 09 12:42:46 PM PDT 24 May 09 12:54:19 PM PDT 24 7277211945 ps
T844 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2306587231 May 09 12:44:27 PM PDT 24 May 09 12:48:32 PM PDT 24 11550272271 ps
T845 /workspace/coverage/default/27.sram_ctrl_lc_escalation.3932917170 May 09 12:42:52 PM PDT 24 May 09 12:42:59 PM PDT 24 3058857274 ps
T846 /workspace/coverage/default/29.sram_ctrl_mem_walk.2174111969 May 09 12:43:09 PM PDT 24 May 09 12:43:16 PM PDT 24 235638482 ps
T847 /workspace/coverage/default/2.sram_ctrl_multiple_keys.2969215326 May 09 12:40:53 PM PDT 24 May 09 12:50:50 PM PDT 24 40894794234 ps
T848 /workspace/coverage/default/11.sram_ctrl_regwen.1801013946 May 09 12:41:32 PM PDT 24 May 09 12:51:08 PM PDT 24 13424895808 ps
T849 /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3704612257 May 09 12:44:27 PM PDT 24 May 09 12:44:49 PM PDT 24 91982373 ps
T850 /workspace/coverage/default/29.sram_ctrl_alert_test.1847717202 May 09 12:43:01 PM PDT 24 May 09 12:43:04 PM PDT 24 14837876 ps
T851 /workspace/coverage/default/21.sram_ctrl_alert_test.1800848042 May 09 12:42:20 PM PDT 24 May 09 12:42:24 PM PDT 24 22985738 ps
T852 /workspace/coverage/default/12.sram_ctrl_stress_all.531923693 May 09 12:41:40 PM PDT 24 May 09 01:31:48 PM PDT 24 39397812075 ps
T853 /workspace/coverage/default/33.sram_ctrl_multiple_keys.121915348 May 09 12:43:21 PM PDT 24 May 09 12:59:12 PM PDT 24 3434803479 ps
T854 /workspace/coverage/default/4.sram_ctrl_lc_escalation.1324871982 May 09 12:41:09 PM PDT 24 May 09 12:41:17 PM PDT 24 1057565047 ps
T855 /workspace/coverage/default/3.sram_ctrl_stress_pipeline.335324547 May 09 12:40:57 PM PDT 24 May 09 12:43:51 PM PDT 24 2040746794 ps
T856 /workspace/coverage/default/44.sram_ctrl_regwen.2405345797 May 09 12:44:35 PM PDT 24 May 09 12:50:44 PM PDT 24 15419681446 ps
T857 /workspace/coverage/default/49.sram_ctrl_regwen.286460993 May 09 03:53:01 PM PDT 24 May 09 04:07:51 PM PDT 24 75891658364 ps
T858 /workspace/coverage/default/4.sram_ctrl_smoke.4011236141 May 09 12:41:06 PM PDT 24 May 09 12:41:16 PM PDT 24 299619962 ps
T859 /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2979294272 May 09 12:43:27 PM PDT 24 May 09 12:43:37 PM PDT 24 509105092 ps
T860 /workspace/coverage/default/16.sram_ctrl_mem_walk.1901300596 May 09 12:42:00 PM PDT 24 May 09 12:42:11 PM PDT 24 457266680 ps
T861 /workspace/coverage/default/12.sram_ctrl_ram_cfg.481081659 May 09 12:41:41 PM PDT 24 May 09 12:41:48 PM PDT 24 31439252 ps
T862 /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1283654929 May 09 12:40:56 PM PDT 24 May 09 12:41:28 PM PDT 24 334784844 ps
T863 /workspace/coverage/default/29.sram_ctrl_lc_escalation.3169781117 May 09 12:43:01 PM PDT 24 May 09 12:43:05 PM PDT 24 227750016 ps
T864 /workspace/coverage/default/47.sram_ctrl_lc_escalation.2371591873 May 09 12:44:48 PM PDT 24 May 09 12:44:56 PM PDT 24 571529116 ps
T865 /workspace/coverage/default/38.sram_ctrl_smoke.3680036977 May 09 12:43:47 PM PDT 24 May 09 12:46:30 PM PDT 24 630846791 ps
T866 /workspace/coverage/default/16.sram_ctrl_bijection.510837243 May 09 12:41:54 PM PDT 24 May 09 12:42:33 PM PDT 24 638730845 ps
T867 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.2982989576 May 09 12:43:18 PM PDT 24 May 09 12:48:29 PM PDT 24 3390306832 ps
T868 /workspace/coverage/default/28.sram_ctrl_executable.3206754606 May 09 12:42:55 PM PDT 24 May 09 12:54:05 PM PDT 24 2988745633 ps
T869 /workspace/coverage/default/11.sram_ctrl_alert_test.1309015738 May 09 12:41:38 PM PDT 24 May 09 12:41:43 PM PDT 24 14115222 ps
T870 /workspace/coverage/default/19.sram_ctrl_multiple_keys.2655983546 May 09 12:42:05 PM PDT 24 May 09 01:00:00 PM PDT 24 33486204293 ps
T871 /workspace/coverage/default/39.sram_ctrl_stress_pipeline.1595726992 May 09 12:44:00 PM PDT 24 May 09 12:48:30 PM PDT 24 3003821963 ps
T872 /workspace/coverage/default/3.sram_ctrl_bijection.3095688118 May 09 12:40:59 PM PDT 24 May 09 12:42:16 PM PDT 24 9518612250 ps
T873 /workspace/coverage/default/28.sram_ctrl_ram_cfg.1446176759 May 09 12:43:09 PM PDT 24 May 09 12:43:13 PM PDT 24 75435198 ps
T874 /workspace/coverage/default/10.sram_ctrl_stress_pipeline.3349002464 May 09 12:41:20 PM PDT 24 May 09 12:46:11 PM PDT 24 12196355792 ps
T875 /workspace/coverage/default/31.sram_ctrl_multiple_keys.404557374 May 09 12:43:10 PM PDT 24 May 09 12:50:04 PM PDT 24 11802296796 ps
T876 /workspace/coverage/default/34.sram_ctrl_executable.829861538 May 09 12:43:31 PM PDT 24 May 09 01:08:32 PM PDT 24 78930467204 ps
T877 /workspace/coverage/default/34.sram_ctrl_ram_cfg.1494564044 May 09 12:43:32 PM PDT 24 May 09 12:43:35 PM PDT 24 83229097 ps
T878 /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.4117199446 May 09 12:40:57 PM PDT 24 May 09 12:47:14 PM PDT 24 59109144310 ps
T879 /workspace/coverage/default/47.sram_ctrl_access_during_key_req.1329799717 May 09 12:44:49 PM PDT 24 May 09 12:50:59 PM PDT 24 1264657971 ps
T880 /workspace/coverage/default/15.sram_ctrl_partial_access.246656320 May 09 12:41:50 PM PDT 24 May 09 12:43:48 PM PDT 24 720027390 ps
T881 /workspace/coverage/default/29.sram_ctrl_mem_partial_access.1257356251 May 09 12:43:04 PM PDT 24 May 09 12:43:10 PM PDT 24 62402921 ps
T882 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.1436388205 May 09 12:44:26 PM PDT 24 May 09 12:48:59 PM PDT 24 5498528488 ps
T883 /workspace/coverage/default/2.sram_ctrl_lc_escalation.3146834601 May 09 12:40:56 PM PDT 24 May 09 12:41:05 PM PDT 24 350854605 ps
T884 /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1959718371 May 09 12:41:51 PM PDT 24 May 09 12:50:43 PM PDT 24 13084201426 ps
T885 /workspace/coverage/default/0.sram_ctrl_ram_cfg.2485815382 May 09 12:40:55 PM PDT 24 May 09 12:41:00 PM PDT 24 50684760 ps
T886 /workspace/coverage/default/44.sram_ctrl_multiple_keys.433911668 May 09 12:44:27 PM PDT 24 May 09 12:50:39 PM PDT 24 9312662815 ps
T887 /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.4291601485 May 09 12:43:22 PM PDT 24 May 09 12:43:43 PM PDT 24 278178750 ps
T888 /workspace/coverage/default/45.sram_ctrl_stress_all.3713075787 May 09 12:44:36 PM PDT 24 May 09 01:31:02 PM PDT 24 8332447837 ps
T889 /workspace/coverage/default/15.sram_ctrl_alert_test.3400373956 May 09 12:41:53 PM PDT 24 May 09 12:41:58 PM PDT 24 15962704 ps
T890 /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.862856565 May 09 12:40:56 PM PDT 24 May 09 12:41:10 PM PDT 24 215384284 ps
T891 /workspace/coverage/default/48.sram_ctrl_ram_cfg.2769742763 May 09 12:45:00 PM PDT 24 May 09 12:45:03 PM PDT 24 290220337 ps
T892 /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.151425721 May 09 12:43:04 PM PDT 24 May 09 12:43:17 PM PDT 24 69843723 ps
T893 /workspace/coverage/default/34.sram_ctrl_stress_all.2815337053 May 09 12:43:28 PM PDT 24 May 09 01:33:57 PM PDT 24 11669498787 ps
T894 /workspace/coverage/default/0.sram_ctrl_lc_escalation.217001350 May 09 12:40:58 PM PDT 24 May 09 12:41:09 PM PDT 24 669348308 ps
T895 /workspace/coverage/default/20.sram_ctrl_bijection.2007790803 May 09 12:42:11 PM PDT 24 May 09 12:43:09 PM PDT 24 12049209527 ps
T896 /workspace/coverage/default/30.sram_ctrl_executable.4027408118 May 09 12:43:11 PM PDT 24 May 09 01:09:50 PM PDT 24 40673737699 ps
T897 /workspace/coverage/default/7.sram_ctrl_alert_test.2515174777 May 09 12:41:19 PM PDT 24 May 09 12:41:22 PM PDT 24 39892676 ps
T898 /workspace/coverage/default/21.sram_ctrl_mem_partial_access.2113832638 May 09 12:42:28 PM PDT 24 May 09 12:42:35 PM PDT 24 472730340 ps
T899 /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.3182763111 May 09 12:42:03 PM PDT 24 May 09 12:45:24 PM PDT 24 1201090910 ps
T900 /workspace/coverage/default/29.sram_ctrl_stress_pipeline.3096513136 May 09 12:43:00 PM PDT 24 May 09 12:44:53 PM PDT 24 4551582858 ps
T901 /workspace/coverage/default/7.sram_ctrl_executable.3736290413 May 09 12:41:15 PM PDT 24 May 09 12:58:52 PM PDT 24 3922223080 ps
T902 /workspace/coverage/default/36.sram_ctrl_regwen.2487401726 May 09 12:43:39 PM PDT 24 May 09 12:47:38 PM PDT 24 9374719463 ps
T903 /workspace/coverage/default/31.sram_ctrl_partial_access.856946491 May 09 12:43:10 PM PDT 24 May 09 12:43:31 PM PDT 24 2036848722 ps
T904 /workspace/coverage/default/34.sram_ctrl_mem_partial_access.634272694 May 09 12:43:31 PM PDT 24 May 09 12:43:36 PM PDT 24 84135753 ps
T905 /workspace/coverage/default/17.sram_ctrl_executable.2371047435 May 09 12:42:02 PM PDT 24 May 09 12:51:13 PM PDT 24 11272659904 ps
T906 /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1320934786 May 09 12:43:07 PM PDT 24 May 09 12:45:38 PM PDT 24 15654735231 ps
T907 /workspace/coverage/default/39.sram_ctrl_max_throughput.1893500600 May 09 12:43:58 PM PDT 24 May 09 12:44:53 PM PDT 24 1114914338 ps
T908 /workspace/coverage/default/34.sram_ctrl_access_during_key_req.592757333 May 09 12:43:29 PM PDT 24 May 09 01:13:44 PM PDT 24 21146212187 ps
T909 /workspace/coverage/default/13.sram_ctrl_partial_access.1210270678 May 09 12:41:38 PM PDT 24 May 09 12:42:56 PM PDT 24 716759538 ps
T910 /workspace/coverage/default/48.sram_ctrl_executable.583140638 May 09 12:44:59 PM PDT 24 May 09 12:53:02 PM PDT 24 8928628016 ps
T911 /workspace/coverage/default/43.sram_ctrl_max_throughput.2490829342 May 09 12:44:32 PM PDT 24 May 09 12:44:40 PM PDT 24 119336042 ps
T912 /workspace/coverage/default/35.sram_ctrl_regwen.4264263744 May 09 12:43:43 PM PDT 24 May 09 01:03:52 PM PDT 24 67650611053 ps
T913 /workspace/coverage/default/32.sram_ctrl_partial_access.701257750 May 09 12:43:25 PM PDT 24 May 09 12:45:01 PM PDT 24 204185512 ps
T914 /workspace/coverage/default/16.sram_ctrl_multiple_keys.1076483399 May 09 12:41:52 PM PDT 24 May 09 12:48:26 PM PDT 24 15183625314 ps
T915 /workspace/coverage/default/41.sram_ctrl_max_throughput.906193064 May 09 12:44:17 PM PDT 24 May 09 12:44:53 PM PDT 24 102926018 ps
T916 /workspace/coverage/default/21.sram_ctrl_bijection.844692650 May 09 12:42:10 PM PDT 24 May 09 12:43:14 PM PDT 24 1172929422 ps
T917 /workspace/coverage/default/36.sram_ctrl_partial_access.2198472902 May 09 12:43:43 PM PDT 24 May 09 12:43:54 PM PDT 24 333938347 ps
T918 /workspace/coverage/default/3.sram_ctrl_mem_walk.3239394875 May 09 12:41:09 PM PDT 24 May 09 12:41:21 PM PDT 24 466260530 ps
T919 /workspace/coverage/default/0.sram_ctrl_max_throughput.3946198882 May 09 12:40:58 PM PDT 24 May 09 12:41:58 PM PDT 24 222267258 ps
T920 /workspace/coverage/default/30.sram_ctrl_partial_access.2382163408 May 09 12:43:01 PM PDT 24 May 09 12:45:35 PM PDT 24 273433426 ps
T921 /workspace/coverage/default/22.sram_ctrl_executable.2044570564 May 09 12:42:21 PM PDT 24 May 09 12:57:36 PM PDT 24 3555803242 ps
T922 /workspace/coverage/default/47.sram_ctrl_smoke.501483634 May 09 12:44:46 PM PDT 24 May 09 12:46:40 PM PDT 24 232737160 ps
T923 /workspace/coverage/default/25.sram_ctrl_max_throughput.2383178756 May 09 12:42:44 PM PDT 24 May 09 12:42:53 PM PDT 24 59104609 ps
T924 /workspace/coverage/default/15.sram_ctrl_max_throughput.3171879372 May 09 12:41:52 PM PDT 24 May 09 12:43:49 PM PDT 24 732766006 ps
T925 /workspace/coverage/default/49.sram_ctrl_mem_partial_access.2373208086 May 09 02:56:08 PM PDT 24 May 09 02:56:12 PM PDT 24 44455149 ps
T926 /workspace/coverage/default/9.sram_ctrl_smoke.2520513305 May 09 12:41:18 PM PDT 24 May 09 12:41:26 PM PDT 24 713584683 ps
T927 /workspace/coverage/default/20.sram_ctrl_smoke.2533293566 May 09 12:42:17 PM PDT 24 May 09 12:42:22 PM PDT 24 1217251497 ps
T928 /workspace/coverage/default/21.sram_ctrl_regwen.610461142 May 09 12:42:20 PM PDT 24 May 09 12:57:57 PM PDT 24 46488206537 ps
T929 /workspace/coverage/default/32.sram_ctrl_mem_partial_access.1522314702 May 09 12:43:20 PM PDT 24 May 09 12:43:26 PM PDT 24 188893442 ps
T95 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3821999554 May 09 12:39:58 PM PDT 24 May 09 12:40:12 PM PDT 24 351598147 ps
T54 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2084583980 May 09 12:39:53 PM PDT 24 May 09 12:40:09 PM PDT 24 849354180 ps
T930 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2485584305 May 09 12:40:04 PM PDT 24 May 09 12:40:21 PM PDT 24 276778595 ps
T931 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.505398822 May 09 12:39:50 PM PDT 24 May 09 12:40:03 PM PDT 24 53503709 ps
T96 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1179617873 May 09 12:39:57 PM PDT 24 May 09 12:40:12 PM PDT 24 238251506 ps
T932 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2928432410 May 09 12:39:44 PM PDT 24 May 09 12:39:54 PM PDT 24 332992856 ps
T55 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2041361288 May 09 12:40:00 PM PDT 24 May 09 12:40:15 PM PDT 24 273033488 ps
T56 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4063550814 May 09 12:39:48 PM PDT 24 May 09 12:40:01 PM PDT 24 469114055 ps
T57 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3255857482 May 09 12:40:07 PM PDT 24 May 09 12:40:21 PM PDT 24 3244870109 ps
T933 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.736924267 May 09 12:40:04 PM PDT 24 May 09 12:40:19 PM PDT 24 134682678 ps
T92 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.824104581 May 09 12:39:51 PM PDT 24 May 09 12:40:04 PM PDT 24 13679104 ps
T58 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2551577162 May 09 12:39:50 PM PDT 24 May 09 12:40:03 PM PDT 24 14754776 ps
T87 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.928726001 May 09 12:39:41 PM PDT 24 May 09 12:39:49 PM PDT 24 18948014 ps
T59 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3182296654 May 09 12:39:55 PM PDT 24 May 09 12:40:09 PM PDT 24 34688021 ps
T93 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1818693976 May 09 12:40:00 PM PDT 24 May 09 12:40:13 PM PDT 24 20767643 ps
T97 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1210823118 May 09 12:39:58 PM PDT 24 May 09 12:40:13 PM PDT 24 2415853948 ps
T60 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1023297501 May 09 12:39:50 PM PDT 24 May 09 12:40:03 PM PDT 24 32461697 ps
T61 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2048846321 May 09 12:39:57 PM PDT 24 May 09 12:40:13 PM PDT 24 2540037737 ps
T934 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3091570676 May 09 12:39:55 PM PDT 24 May 09 12:40:10 PM PDT 24 165006056 ps
T62 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.510288780 May 09 12:39:44 PM PDT 24 May 09 12:39:52 PM PDT 24 92010733 ps
T88 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.409913606 May 09 12:40:05 PM PDT 24 May 09 12:40:18 PM PDT 24 19636932 ps
T935 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.32682290 May 09 12:40:05 PM PDT 24 May 09 12:40:20 PM PDT 24 78791868 ps
T936 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.4023850140 May 09 12:39:45 PM PDT 24 May 09 12:39:54 PM PDT 24 17599376 ps
T937 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1647102257 May 09 12:39:52 PM PDT 24 May 09 12:40:05 PM PDT 24 16162416 ps
T89 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3256080727 May 09 12:39:55 PM PDT 24 May 09 12:40:11 PM PDT 24 1735659424 ps
T938 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3750694835 May 09 12:39:54 PM PDT 24 May 09 12:40:07 PM PDT 24 151533029 ps
T63 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2916635847 May 09 12:39:45 PM PDT 24 May 09 12:39:54 PM PDT 24 129524923 ps
T939 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3602653609 May 09 12:40:13 PM PDT 24 May 09 12:40:25 PM PDT 24 26877896 ps
T940 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2431216741 May 09 12:39:56 PM PDT 24 May 09 12:40:12 PM PDT 24 1596228837 ps
T941 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.932878714 May 09 12:39:51 PM PDT 24 May 09 12:40:04 PM PDT 24 18967339 ps
T66 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3270149359 May 09 12:40:05 PM PDT 24 May 09 12:40:21 PM PDT 24 5295838618 ps
T942 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3376200034 May 09 12:39:53 PM PDT 24 May 09 12:40:06 PM PDT 24 22772078 ps
T943 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.808808661 May 09 12:40:04 PM PDT 24 May 09 12:40:17 PM PDT 24 26927501 ps
T118 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.790441451 May 09 12:40:56 PM PDT 24 May 09 12:41:02 PM PDT 24 263282397 ps
T944 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1454159918 May 09 12:39:55 PM PDT 24 May 09 12:40:09 PM PDT 24 19134755 ps
T945 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1040500349 May 09 12:40:00 PM PDT 24 May 09 12:40:13 PM PDT 24 44205009 ps
T946 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1160473271 May 09 12:39:53 PM PDT 24 May 09 12:40:06 PM PDT 24 14956354 ps
T947 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3499556856 May 09 12:39:50 PM PDT 24 May 09 12:40:02 PM PDT 24 268267779 ps
T124 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.835817237 May 09 12:39:54 PM PDT 24 May 09 12:40:09 PM PDT 24 449323989 ps
T948 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2746028776 May 09 12:40:08 PM PDT 24 May 09 12:40:23 PM PDT 24 290681950 ps
T67 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.805527495 May 09 12:39:55 PM PDT 24 May 09 12:40:10 PM PDT 24 1996234293 ps
T122 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2505945735 May 09 12:39:44 PM PDT 24 May 09 12:39:54 PM PDT 24 161283699 ps
T949 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1556889406 May 09 12:40:01 PM PDT 24 May 09 12:40:15 PM PDT 24 33460132 ps
T950 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3018587650 May 09 12:40:09 PM PDT 24 May 09 12:40:21 PM PDT 24 16560305 ps
T951 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2730929917 May 09 12:39:56 PM PDT 24 May 09 12:40:09 PM PDT 24 83134966 ps
T952 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3876451534 May 09 12:40:09 PM PDT 24 May 09 12:40:21 PM PDT 24 14409897 ps
T953 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.525862894 May 09 12:40:57 PM PDT 24 May 09 12:41:03 PM PDT 24 45101955 ps
T954 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2294387605 May 09 12:39:53 PM PDT 24 May 09 12:40:07 PM PDT 24 136108271 ps
T955 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.967620214 May 09 12:39:51 PM PDT 24 May 09 12:40:06 PM PDT 24 44620570 ps
T956 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2112216810 May 09 12:39:57 PM PDT 24 May 09 12:40:12 PM PDT 24 39472116 ps
T957 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.721209347 May 09 12:39:49 PM PDT 24 May 09 12:40:02 PM PDT 24 94745692 ps
T958 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.468642721 May 09 12:40:03 PM PDT 24 May 09 12:40:19 PM PDT 24 231950166 ps
T68 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3107283988 May 09 12:39:55 PM PDT 24 May 09 12:40:12 PM PDT 24 386113561 ps
T959 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2405069314 May 09 12:40:03 PM PDT 24 May 09 12:40:17 PM PDT 24 61645785 ps
T960 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.958146018 May 09 12:40:56 PM PDT 24 May 09 12:41:00 PM PDT 24 48424992 ps
T79 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.859502953 May 09 12:39:52 PM PDT 24 May 09 12:40:05 PM PDT 24 24503690 ps
T961 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2224766200 May 09 12:39:48 PM PDT 24 May 09 12:40:00 PM PDT 24 43310814 ps
T69 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3793621664 May 09 12:39:55 PM PDT 24 May 09 12:40:09 PM PDT 24 14746710 ps
T962 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1323012952 May 09 12:40:05 PM PDT 24 May 09 12:40:18 PM PDT 24 19569994 ps
T963 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2900778944 May 09 12:39:46 PM PDT 24 May 09 12:39:56 PM PDT 24 178689898 ps
T964 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1966430081 May 09 12:39:50 PM PDT 24 May 09 12:40:02 PM PDT 24 94021373 ps
T965 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3395782426 May 09 12:39:55 PM PDT 24 May 09 12:40:09 PM PDT 24 39068094 ps
T966 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2831378956 May 09 12:40:02 PM PDT 24 May 09 12:40:16 PM PDT 24 116099840 ps
T967 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3782377739 May 09 12:40:11 PM PDT 24 May 09 12:40:23 PM PDT 24 76393985 ps
T80 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.770057114 May 09 12:40:09 PM PDT 24 May 09 12:40:21 PM PDT 24 41212447 ps
T968 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.4191570111 May 09 12:40:56 PM PDT 24 May 09 12:41:05 PM PDT 24 335568825 ps
T969 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.675294949 May 09 12:40:57 PM PDT 24 May 09 12:41:02 PM PDT 24 15364553 ps
T970 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3321703186 May 09 12:40:04 PM PDT 24 May 09 12:40:17 PM PDT 24 16455189 ps
T81 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2783623090 May 09 12:39:49 PM PDT 24 May 09 12:40:02 PM PDT 24 29497260 ps
T971 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2456245930 May 09 12:39:57 PM PDT 24 May 09 12:40:12 PM PDT 24 179071410 ps
T119 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2355204008 May 09 12:40:55 PM PDT 24 May 09 12:41:00 PM PDT 24 438869163 ps
T972 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3913116390 May 09 12:39:46 PM PDT 24 May 09 12:39:58 PM PDT 24 276538041 ps
T82 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2372672949 May 09 12:39:48 PM PDT 24 May 09 12:40:01 PM PDT 24 1557686477 ps
T123 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3898343421 May 09 12:39:54 PM PDT 24 May 09 12:40:09 PM PDT 24 675436376 ps
T973 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.629529204 May 09 12:40:02 PM PDT 24 May 09 12:40:16 PM PDT 24 82837672 ps
T974 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.464827214 May 09 12:40:00 PM PDT 24 May 09 12:40:13 PM PDT 24 33419930 ps
T975 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3058747332 May 09 12:39:50 PM PDT 24 May 09 12:40:06 PM PDT 24 469835397 ps
T976 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.313883850 May 09 12:39:51 PM PDT 24 May 09 12:40:05 PM PDT 24 53935025 ps
T977 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.91775400 May 09 12:39:50 PM PDT 24 May 09 12:40:04 PM PDT 24 157761098 ps
T978 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1482702824 May 09 12:40:03 PM PDT 24 May 09 12:40:18 PM PDT 24 33418427 ps
T979 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.4279106789 May 09 12:39:56 PM PDT 24 May 09 12:40:12 PM PDT 24 814882892 ps
T980 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2727847395 May 09 12:39:55 PM PDT 24 May 09 12:40:09 PM PDT 24 13547032 ps
T981 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2078873650 May 09 12:40:54 PM PDT 24 May 09 12:40:57 PM PDT 24 39304404 ps
T982 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1144944819 May 09 12:39:59 PM PDT 24 May 09 12:40:16 PM PDT 24 535865539 ps
T983 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3326449027 May 09 12:40:54 PM PDT 24 May 09 12:40:59 PM PDT 24 360161667 ps
T83 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2283663233 May 09 12:39:55 PM PDT 24 May 09 12:40:10 PM PDT 24 833048783 ps
T984 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2053121180 May 09 12:39:52 PM PDT 24 May 09 12:40:08 PM PDT 24 42554303 ps
T985 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3284745162 May 09 12:39:53 PM PDT 24 May 09 12:40:07 PM PDT 24 69567048 ps
T986 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.4186186970 May 09 12:39:53 PM PDT 24 May 09 12:40:08 PM PDT 24 114810188 ps
T987 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.63319071 May 09 12:39:54 PM PDT 24 May 09 12:40:08 PM PDT 24 21064851 ps
T988 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3038804761 May 09 12:40:56 PM PDT 24 May 09 12:41:00 PM PDT 24 25808176 ps
T125 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.544275980 May 09 12:40:04 PM PDT 24 May 09 12:40:19 PM PDT 24 1407512286 ps
T989 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1658613303 May 09 12:39:53 PM PDT 24 May 09 12:40:07 PM PDT 24 88314968 ps
T84 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4190469533 May 09 12:39:54 PM PDT 24 May 09 12:40:09 PM PDT 24 627147204 ps
T990 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.790119471 May 09 12:40:00 PM PDT 24 May 09 12:40:15 PM PDT 24 89591997 ps
T991 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1119245928 May 09 12:39:50 PM PDT 24 May 09 12:40:03 PM PDT 24 45639765 ps
T85 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3938173894 May 09 12:40:13 PM PDT 24 May 09 12:40:25 PM PDT 24 2456534491 ps
T992 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1229685215 May 09 12:39:49 PM PDT 24 May 09 12:40:02 PM PDT 24 52092887 ps
T993 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.337661690 May 09 12:39:52 PM PDT 24 May 09 12:40:05 PM PDT 24 11298550 ps
T120 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3134312913 May 09 12:40:09 PM PDT 24 May 09 12:40:23 PM PDT 24 1229906167 ps
T994 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.952602998 May 09 12:39:51 PM PDT 24 May 09 12:40:03 PM PDT 24 77351448 ps
T995 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3003315615 May 09 12:40:05 PM PDT 24 May 09 12:40:19 PM PDT 24 215918106 ps
T996 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2586859165 May 09 12:39:50 PM PDT 24 May 09 12:40:04 PM PDT 24 313931130 ps
T997 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2215395365 May 09 12:39:53 PM PDT 24 May 09 12:40:07 PM PDT 24 32541253 ps
T998 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.249901504 May 09 12:39:46 PM PDT 24 May 09 12:39:55 PM PDT 24 18060360 ps
T999 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3015938206 May 09 12:39:51 PM PDT 24 May 09 12:40:04 PM PDT 24 14433455 ps
T121 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.400013639 May 09 12:40:10 PM PDT 24 May 09 12:40:24 PM PDT 24 509255407 ps
T1000 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3487369258 May 09 12:40:56 PM PDT 24 May 09 12:41:02 PM PDT 24 27846001 ps
T1001 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2284824939 May 09 12:39:52 PM PDT 24 May 09 12:40:05 PM PDT 24 60951916 ps
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