Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13572768	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

56225125

1

T2

183515

T3

40960

T4

170506

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34789574	1			T2	100714		T3	20480		T4	93912
values[0x0]	16140834	1			T2	48766		T3	10128		T4	45160
values[0x1]	18867485	1			T2	52304		T3	10352		T4	48613

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6763595	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

63034298

1

T2

192801

T3

40960

T4

179232

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	255151	1			T2	729		T3	159		T4	699
valid_sources[0x01]	286749	1			T2	916		T3	154		T4	781
valid_sources[0x02]	256889	1			T2	816		T3	175		T4	719
valid_sources[0x03]	270731	1			T2	1164		T3	155		T4	750
valid_sources[0x04]	377390	1			T2	790		T3	169		T4	707
valid_sources[0x05]	248515	1			T2	888		T3	182		T4	712
valid_sources[0x06]	253424	1			T2	796		T3	137		T4	725
valid_sources[0x07]	268458	1			T2	647		T3	133		T4	727
valid_sources[0x08]	290250	1			T2	684		T3	141		T4	733
valid_sources[0x09]	250722	1			T2	697		T3	167		T4	695
valid_sources[0x0a]	271162	1			T2	714		T3	183		T4	754
valid_sources[0x0b]	271919	1			T2	703		T3	140		T4	726
valid_sources[0x0c]	277817	1			T2	1075		T3	162		T4	763
valid_sources[0x0d]	285201	1			T2	715		T3	163		T4	789
valid_sources[0x0e]	251853	1			T2	792		T3	149		T4	753
valid_sources[0x0f]	290747	1			T2	736		T3	163		T4	726
valid_sources[0x10]	242002	1			T2	916		T3	150		T4	759
valid_sources[0x11]	253477	1			T2	691		T3	152		T4	756
valid_sources[0x12]	262208	1			T2	693		T3	164		T4	784
valid_sources[0x13]	261459	1			T2	974		T3	136		T4	710
valid_sources[0x14]	307359	1			T2	666		T3	195		T4	777
valid_sources[0x15]	272392	1			T2	1010		T3	159		T4	735
valid_sources[0x16]	270526	1			T2	637		T3	148		T4	763
valid_sources[0x17]	247507	1			T2	775		T3	145		T4	714
valid_sources[0x18]	259948	1			T2	871		T3	148		T4	740
valid_sources[0x19]	248250	1			T2	884		T3	159		T4	689
valid_sources[0x1a]	259432	1			T2	809		T3	164		T4	736
valid_sources[0x1b]	309609	1			T2	698		T3	156		T4	761
valid_sources[0x1c]	246589	1			T2	1023		T3	161		T4	734
valid_sources[0x1d]	279654	1			T2	806		T3	145		T4	723
valid_sources[0x1e]	252523	1			T2	704		T3	149		T4	745
valid_sources[0x1f]	277708	1			T2	1006		T3	182		T4	740
valid_sources[0x20]	313612	1			T2	869		T3	190		T4	695
valid_sources[0x21]	249013	1			T2	828		T3	140		T4	766
valid_sources[0x22]	246372	1			T2	625		T3	151		T4	751
valid_sources[0x23]	238542	1			T2	728		T3	166		T4	701
valid_sources[0x24]	280184	1			T2	620		T3	164		T4	729
valid_sources[0x25]	270942	1			T2	879		T3	171		T4	688
valid_sources[0x26]	261643	1			T2	852		T3	155		T4	731
valid_sources[0x27]	264826	1			T2	824		T3	141		T4	696
valid_sources[0x28]	258119	1			T2	796		T3	189		T4	773
valid_sources[0x29]	260597	1			T2	967		T3	174		T4	706
valid_sources[0x2a]	290288	1			T2	885		T3	160		T4	701
valid_sources[0x2b]	238604	1			T2	800		T3	164		T4	732
valid_sources[0x2c]	264404	1			T2	779		T3	176		T4	778
valid_sources[0x2d]	254803	1			T2	636		T3	160		T4	716
valid_sources[0x2e]	305802	1			T2	931		T3	168		T4	776
valid_sources[0x2f]	260996	1			T2	787		T3	136		T4	764
valid_sources[0x30]	360715	1			T2	643		T3	171		T4	718
valid_sources[0x31]	252288	1			T2	844		T3	186		T4	771
valid_sources[0x32]	236171	1			T2	779		T3	174		T4	760
valid_sources[0x33]	243196	1			T2	848		T3	149		T4	697
valid_sources[0x34]	257875	1			T2	644		T3	169		T4	763
valid_sources[0x35]	268572	1			T2	574		T3	162		T4	764
valid_sources[0x36]	284838	1			T2	768		T3	183		T4	753
valid_sources[0x37]	261205	1			T2	785		T3	137		T4	737
valid_sources[0x38]	284397	1			T2	769		T3	138		T4	685
valid_sources[0x39]	249934	1			T2	949		T3	157		T4	741
valid_sources[0x3a]	310448	1			T2	786		T3	155		T4	752
valid_sources[0x3b]	247243	1			T2	789		T3	143		T4	755
valid_sources[0x3c]	243867	1			T2	804		T3	147		T4	743
valid_sources[0x3d]	261791	1			T2	664		T3	163		T4	754
valid_sources[0x3e]	343192	1			T2	819		T3	150		T4	717
valid_sources[0x3f]	250406	1			T2	909		T3	177		T4	772
valid_sources[0x40]	280482	1			T2	797		T3	162		T4	780
valid_sources[0x41]	325457	1			T2	596		T3	137		T4	712
valid_sources[0x42]	274988	1			T2	692		T3	152		T4	756
valid_sources[0x43]	244423	1			T2	798		T3	167		T4	724
valid_sources[0x44]	321894	1			T2	639		T3	157		T4	744
valid_sources[0x45]	266568	1			T2	971		T3	154		T4	712
valid_sources[0x46]	264190	1			T2	621		T3	184		T4	739
valid_sources[0x47]	236658	1			T2	474		T3	155		T4	689
valid_sources[0x48]	255980	1			T2	852		T3	168		T4	723
valid_sources[0x49]	275206	1			T2	773		T3	151		T4	705
valid_sources[0x4a]	239789	1			T2	759		T3	180		T4	763
valid_sources[0x4b]	283896	1			T2	940		T3	151		T4	722
valid_sources[0x4c]	251144	1			T2	736		T3	147		T4	728
valid_sources[0x4d]	273426	1			T2	493		T3	167		T4	751
valid_sources[0x4e]	301828	1			T2	838		T3	156		T4	687
valid_sources[0x4f]	378550	1			T2	1080		T3	162		T4	781
valid_sources[0x50]	260414	1			T2	867		T3	160		T4	732
valid_sources[0x51]	321283	1			T2	938		T3	197		T4	740
valid_sources[0x52]	239296	1			T2	911		T3	165		T4	760
valid_sources[0x53]	306504	1			T2	888		T3	151		T4	736
valid_sources[0x54]	335429	1			T2	783		T3	164		T4	701
valid_sources[0x55]	280876	1			T2	666		T3	157		T4	782
valid_sources[0x56]	333525	1			T2	791		T3	163		T4	725
valid_sources[0x57]	253720	1			T2	922		T3	162		T4	716
valid_sources[0x58]	250342	1			T2	543		T3	153		T4	708
valid_sources[0x59]	239249	1			T2	815		T3	170		T4	765
valid_sources[0x5a]	255889	1			T2	769		T3	139		T4	700
valid_sources[0x5b]	256019	1			T2	1030		T3	144		T4	741
valid_sources[0x5c]	265698	1			T2	742		T3	141		T4	698
valid_sources[0x5d]	334953	1			T2	865		T3	165		T4	795
valid_sources[0x5e]	278251	1			T2	566		T3	168		T4	799
valid_sources[0x5f]	263247	1			T2	899		T3	177		T4	744
valid_sources[0x60]	361828	1			T2	641		T3	171		T4	704
valid_sources[0x61]	249261	1			T2	695		T3	161		T4	758
valid_sources[0x62]	292058	1			T2	724		T3	135		T4	716
valid_sources[0x63]	241545	1			T2	517		T3	145		T4	754
valid_sources[0x64]	292471	1			T2	719		T3	170		T4	699
valid_sources[0x65]	240342	1			T2	1040		T3	141		T4	757
valid_sources[0x66]	252230	1			T2	825		T3	150		T4	727
valid_sources[0x67]	274733	1			T2	841		T3	161		T4	674
valid_sources[0x68]	266382	1			T2	751		T3	173		T4	721
valid_sources[0x69]	277811	1			T2	774		T3	150		T4	691
valid_sources[0x6a]	255739	1			T2	740		T3	198		T4	729
valid_sources[0x6b]	247606	1			T2	611		T3	152		T4	744
valid_sources[0x6c]	292418	1			T2	738		T3	159		T4	732
valid_sources[0x6d]	261695	1			T2	737		T3	157		T4	733
valid_sources[0x6e]	299080	1			T2	803		T3	168		T4	716
valid_sources[0x6f]	252066	1			T2	927		T3	185		T4	712
valid_sources[0x70]	271670	1			T2	790		T3	159		T4	723
valid_sources[0x71]	254460	1			T2	716		T3	168		T4	707
valid_sources[0x72]	243506	1			T2	954		T3	162		T4	711
valid_sources[0x73]	298903	1			T2	831		T3	160		T4	745
valid_sources[0x74]	302895	1			T2	720		T3	172		T4	736
valid_sources[0x75]	274283	1			T2	803		T3	156		T4	729
valid_sources[0x76]	297100	1			T2	1193		T3	140		T4	729
valid_sources[0x77]	345585	1			T2	691		T3	167		T4	763
valid_sources[0x78]	284854	1			T2	548		T3	135		T4	705
valid_sources[0x79]	246481	1			T2	923		T3	140		T4	737
valid_sources[0x7a]	291140	1			T2	846		T3	188		T4	738
valid_sources[0x7b]	242832	1			T2	613		T3	160		T4	746
valid_sources[0x7c]	317992	1			T2	646		T3	159		T4	760
valid_sources[0x7d]	250132	1			T2	593		T3	148		T4	732
valid_sources[0x7e]	277869	1			T2	757		T3	181		T4	701
valid_sources[0x7f]	252294	1			T2	825		T3	163		T4	714
valid_sources[0x80]	294837	1			T2	692		T3	146		T4	734

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28008817

1

T2

91550

T3

20480

T4

85353

values[0x0]

all_enables

biggest_size

14104045

1

T2

46023

T3

10128

T4

42538

values[0x1]

all_enables

biggest_size

14112263

1

T2

45942

T3

10352

T4

42615

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34098	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

140104

1

T2

35

T3

4

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	50920	1			T2	20		T5	30		T11	21
values[0x0]	59945	1			T1	1		T2	39		T3	12
values[0x1]	63337	1			T2	46		T3	8		T4	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25871	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

148331

1

T2

46

T3

5

T4

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	572	1			T21	17		T29	9		T122	1
valid_sources[0x01]	995	1			T12	82		T21	15		T6	2
valid_sources[0x02]	450	1			T11	3		T21	11		T129	1
valid_sources[0x03]	508	1			T21	10		T6	5		T120	1
valid_sources[0x04]	580	1			T21	16		T34	2		T134	1
valid_sources[0x05]	448	1			T10	1		T12	1		T15	1
valid_sources[0x06]	908	1			T12	96		T21	14		T38	204
valid_sources[0x07]	555	1			T12	3		T21	14		T27	2
valid_sources[0x08]	652	1			T21	10		T6	2		T71	1
valid_sources[0x09]	664	1			T21	20		T135	1		T6	4
valid_sources[0x0a]	774	1			T21	19		T29	5		T52	1
valid_sources[0x0b]	543	1			T24	2		T21	23		T8	1
valid_sources[0x0c]	854	1			T50	2		T21	19		T122	1
valid_sources[0x0d]	765	1			T21	10		T87	1		T29	132
valid_sources[0x0e]	575	1			T21	21		T8	3		T70	3
valid_sources[0x0f]	473	1			T21	14		T6	2		T124	2
valid_sources[0x10]	614	1			T21	26		T29	1		T120	1
valid_sources[0x11]	579	1			T12	104		T21	17		T7	9
valid_sources[0x12]	584	1			T21	17		T6	5		T29	9
valid_sources[0x13]	622	1			T21	7		T136	1		T29	93
valid_sources[0x14]	577	1			T21	16		T6	1		T52	1
valid_sources[0x15]	894	1			T21	28		T6	1		T136	1
valid_sources[0x16]	721	1			T5	20		T21	23		T27	1
valid_sources[0x17]	505	1			T21	14		T6	1		T29	2
valid_sources[0x18]	728	1			T21	13		T27	1		T6	1
valid_sources[0x19]	716	1			T11	42		T21	1		T135	1
valid_sources[0x1a]	816	1			T12	1		T21	6		T42	1
valid_sources[0x1b]	741	1			T19	5		T21	9		T137	1
valid_sources[0x1c]	1139	1			T12	130		T21	17		T42	3
valid_sources[0x1d]	469	1			T12	9		T21	10		T87	1
valid_sources[0x1e]	551	1			T20	2		T21	11		T29	1
valid_sources[0x1f]	1256	1			T24	1		T21	12		T135	1
valid_sources[0x20]	629	1			T12	186		T21	5		T135	1
valid_sources[0x21]	490	1			T21	11		T122	1		T42	5
valid_sources[0x22]	709	1			T21	19		T29	1		T138	1
valid_sources[0x23]	567	1			T20	2		T21	8		T88	1
valid_sources[0x24]	528	1			T20	1		T21	7		T136	1
valid_sources[0x25]	765	1			T10	1		T20	1		T21	5
valid_sources[0x26]	633	1			T21	17		T29	3		T52	1
valid_sources[0x27]	574	1			T12	69		T21	18		T6	2
valid_sources[0x28]	761	1			T21	33		T132	1		T139	4
valid_sources[0x29]	577	1			T21	4		T120	1		T72	18
valid_sources[0x2a]	471	1			T20	1		T21	21		T6	1
valid_sources[0x2b]	482	1			T21	19		T70	2		T42	2
valid_sources[0x2c]	702	1			T12	160		T21	16		T29	2
valid_sources[0x2d]	529	1			T21	13		T6	2		T124	2
valid_sources[0x2e]	895	1			T21	15		T29	2		T122	1
valid_sources[0x2f]	888	1			T12	10		T21	23		T134	4
valid_sources[0x30]	475	1			T21	15		T29	5		T120	1
valid_sources[0x31]	1160	1			T10	1		T12	177		T21	17
valid_sources[0x32]	505	1			T21	21		T124	1		T122	5
valid_sources[0x33]	682	1			T20	1		T21	8		T134	1
valid_sources[0x34]	517	1			T12	2		T21	15		T42	1
valid_sources[0x35]	585	1			T21	15		T29	143		T52	1
valid_sources[0x36]	514	1			T21	11		T136	1		T29	1
valid_sources[0x37]	683	1			T21	22		T140	1		T42	3
valid_sources[0x38]	877	1			T4	2		T21	11		T141	1
valid_sources[0x39]	686	1			T21	22		T7	1		T29	113
valid_sources[0x3a]	732	1			T21	16		T6	4		T35	1
valid_sources[0x3b]	734	1			T12	80		T21	18		T29	2
valid_sources[0x3c]	733	1			T12	113		T21	12		T70	1
valid_sources[0x3d]	603	1			T21	10		T29	121		T142	1
valid_sources[0x3e]	828	1			T21	16		T124	1		T42	1
valid_sources[0x3f]	1071	1			T21	7		T29	64		T52	1
valid_sources[0x40]	454	1			T12	5		T51	2		T21	22
valid_sources[0x41]	882	1			T3	20		T21	15		T8	8
valid_sources[0x42]	485	1			T10	2		T21	13		T143	1
valid_sources[0x43]	664	1			T21	18		T120	1		T69	1
valid_sources[0x44]	501	1			T10	2		T12	3		T21	11
valid_sources[0x45]	684	1			T21	7		T29	2		T141	1
valid_sources[0x46]	1058	1			T12	105		T21	8		T6	2
valid_sources[0x47]	565	1			T21	13		T29	1		T122	2
valid_sources[0x48]	601	1			T21	4		T27	1		T52	1
valid_sources[0x49]	716	1			T21	12		T29	196		T120	1
valid_sources[0x4a]	568	1			T15	1		T21	2		T6	6
valid_sources[0x4b]	831	1			T2	105		T21	2		T6	2
valid_sources[0x4c]	760	1			T21	23		T29	5		T122	1
valid_sources[0x4d]	477	1			T9	1		T21	5		T29	1
valid_sources[0x4e]	570	1			T21	6		T136	1		T52	1
valid_sources[0x4f]	717	1			T21	14		T8	4		T29	24
valid_sources[0x50]	644	1			T21	20		T135	1		T124	1
valid_sources[0x51]	659	1			T21	10		T6	5		T29	4
valid_sources[0x52]	669	1			T21	8		T29	34		T124	1
valid_sources[0x53]	679	1			T12	4		T21	26		T135	1
valid_sources[0x54]	600	1			T21	17		T29	1		T120	1
valid_sources[0x55]	442	1			T21	10		T29	18		T144	2
valid_sources[0x56]	485	1			T21	12		T6	2		T42	1
valid_sources[0x57]	770	1			T12	106		T21	9		T122	2
valid_sources[0x58]	685	1			T10	1		T49	2		T21	12
valid_sources[0x59]	522	1			T12	3		T21	15		T27	1
valid_sources[0x5a]	704	1			T21	10		T135	1		T124	1
valid_sources[0x5b]	749	1			T10	3		T21	11		T27	1
valid_sources[0x5c]	677	1			T21	22		T27	1		T8	10
valid_sources[0x5d]	540	1			T21	8		T135	1		T6	3
valid_sources[0x5e]	603	1			T21	16		T52	1		T42	1
valid_sources[0x5f]	550	1			T12	3		T21	10		T135	1
valid_sources[0x60]	523	1			T10	5		T21	10		T27	1
valid_sources[0x61]	560	1			T21	22		T87	1		T145	1
valid_sources[0x62]	434	1			T21	15		T136	2		T42	2
valid_sources[0x63]	830	1			T11	13		T12	92		T20	3
valid_sources[0x64]	536	1			T21	14		T120	1		T42	3
valid_sources[0x65]	695	1			T21	10		T29	1		T120	1
valid_sources[0x66]	896	1			T10	1		T12	195		T21	25
valid_sources[0x67]	536	1			T21	7		T52	1		T42	4
valid_sources[0x68]	828	1			T11	32		T21	23		T6	2
valid_sources[0x69]	770	1			T21	11		T27	1		T29	243
valid_sources[0x6a]	556	1			T21	12		T36	4		T42	4
valid_sources[0x6b]	855	1			T10	2		T21	7		T43	17
valid_sources[0x6c]	803	1			T21	24		T43	7		T146	1
valid_sources[0x6d]	1295	1			T21	8		T135	1		T6	1
valid_sources[0x6e]	605	1			T21	8		T27	1		T136	1
valid_sources[0x6f]	770	1			T20	1		T21	18		T29	3
valid_sources[0x70]	1198	1			T5	17		T12	276		T21	18
valid_sources[0x71]	498	1			T10	3		T21	8		T52	1
valid_sources[0x72]	471	1			T21	8		T6	2		T122	1
valid_sources[0x73]	553	1			T4	1		T20	1		T21	10
valid_sources[0x74]	746	1			T21	21		T52	1		T145	1
valid_sources[0x75]	556	1			T21	18		T6	1		T134	1
valid_sources[0x76]	654	1			T21	8		T135	1		T139	3
valid_sources[0x77]	658	1			T21	18		T29	1		T147	1
valid_sources[0x78]	682	1			T21	15		T6	1		T122	1
valid_sources[0x79]	460	1			T21	20		T120	1		T148	2
valid_sources[0x7a]	1032	1			T12	85		T19	11		T21	6
valid_sources[0x7b]	788	1			T21	23		T8	6		T120	1
valid_sources[0x7c]	740	1			T20	1		T21	22		T6	1
valid_sources[0x7d]	540	1			T12	1		T21	7		T143	1
valid_sources[0x7e]	546	1			T21	13		T29	3		T144	1
valid_sources[0x7f]	551	1			T21	18		T142	1		T42	3
valid_sources[0x80]	782	1			T12	82		T20	1		T21	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

38587

1

T2

12

T5

20

T11

12

values[0x0]

all_enables

biggest_size

51944

1

T2

17

T3

4

T5

4

values[0x1]

all_enables

biggest_size

49573

1

T2

6

T4

1

T5

4