Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13294976

1

T2

14618

T4

17179

T5

21

full_word

51511829

1

T2

146914

T3

40960

T4

170506

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	64806475	1			T2	161532		T3	40960		T4	187685
auto[TlIntgErrCmd]	109	1			T92	6		T93	4		T94	3
auto[TlIntgErrData]	115	1			T92	1		T93	9		T94	6
auto[TlIntgErrBoth]	106	1			T92	3		T93	7		T94	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29748248

1

T2

60462

T3

20480

T4

93912

auto[1]

35058557

1

T2

101070

T3

20480

T4

93773

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6358012	1			T2	5513		T4	8559		T5	11
auto[TlIntgErrNone]	partial	auto[1]	6936664	1			T2	9105		T4	8620		T5	10
auto[TlIntgErrNone]	full_word	auto[0]	23390075	1			T2	54949		T3	20480		T4	85353
auto[TlIntgErrNone]	full_word	auto[1]	28121724	1			T2	91965		T3	20480		T4	85153
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T92	3		T94	1		T109	5
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T92	2		T93	4		T94	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T117	1		T118	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T92	1		T114	1		T111	1
auto[TlIntgErrData]	partial	auto[0]	57	1			T92	1		T93	6		T94	6
auto[TlIntgErrData]	partial	auto[1]	43	1			T93	2		T109	1		T111	1
auto[TlIntgErrData]	full_word	auto[0]	10	1			T93	1		T111	1		T112	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T114	1		T110	2		T119	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T92	1		T93	2		T94	1
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T92	1		T93	5		T114	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T112	1		T117	1		T113	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T92	1		T116	1		-	-