Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	722956	1			T6	6456		T14	4		T16	7596
auto[1]	9798982	1			T2	300		T4	78873		T5	8
auto[2]	593931	1			T6	4042		T14	4		T16	6899
auto[3]	9678862	1			T2	265		T4	78821		T5	8

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13605886	1			T2	414		T4	130099		T5	11
auto[1]	1986188	1			T2	73		T4	13076		T5	3
auto[2]	1965050	1			T2	72		T4	13220		T5	2
auto[3]	3237607	1			T2	6		T4	1299		T9	87

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8056119

1

T2

565

T5

16

T9

173

auto[1]

12738612

1

T4

157694

T10

111

T11

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	277733	1			T6	5295		T16	6299		T38	18052
auto[0]	auto[0]	auto[1]	28303	1			T6	537		T16	615		T38	1850
auto[0]	auto[0]	auto[2]	28123	1			T6	565		T14	1		T16	620
auto[0]	auto[0]	auto[3]	8479	1			T6	56		T14	3		T16	57
auto[0]	auto[1]	auto[0]	3034531	1			T2	216		T5	4		T9	7
auto[0]	auto[1]	auto[1]	320847	1			T2	59		T5	3		T9	12
auto[0]	auto[1]	auto[2]	305946	1			T2	20		T5	1		T9	33
auto[0]	auto[1]	auto[3]	67931	1			T2	5		T9	53		T10	368
auto[0]	auto[2]	auto[0]	242476	1			T6	3149		T16	5765		T38	16450
auto[0]	auto[2]	auto[1]	24907	1			T6	315		T14	1		T16	540
auto[0]	auto[2]	auto[2]	22416	1			T6	537		T16	530		T38	1550
auto[0]	auto[2]	auto[3]	6361	1			T6	37		T14	3		T16	58
auto[0]	auto[3]	auto[0]	2999741	1			T2	198		T5	7		T9	7
auto[0]	auto[3]	auto[1]	301815	1			T2	14		T9	14		T10	4220
auto[0]	auto[3]	auto[2]	316009	1			T2	52		T5	1		T9	13
auto[0]	auto[3]	auto[3]	70501	1			T2	1		T9	34		T10	375
auto[1]	auto[0]	auto[0]	12607	1			T6	2		T16	3		T38	19
auto[1]	auto[0]	auto[1]	56388	1			T16	1		T38	3		T129	1
auto[1]	auto[0]	auto[2]	56299	1			T6	1		T16	1		T38	1
auto[1]	auto[0]	auto[3]	255024	1			T38	1		T126	18003		T130	1
auto[1]	auto[1]	auto[0]	3514016	1			T4	65146		T10	46		T11	1
auto[1]	auto[1]	auto[1]	622453	1			T4	6497		T10	4		T20	1
auto[1]	auto[1]	auto[2]	584778	1			T4	6620		T10	7		T20	3
auto[1]	auto[1]	auto[3]	1348480	1			T4	610		T15	771		T6	1
auto[1]	auto[2]	auto[0]	11657	1			T6	4		T16	4		T38	20
auto[1]	auto[2]	auto[1]	51119	1			T16	1		T126	3676		T131	1
auto[1]	auto[2]	auto[2]	42680	1			T126	2785		T131	1		T127	4316
auto[1]	auto[2]	auto[3]	192315	1			T16	1		T126	12143		T127	20066
auto[1]	auto[3]	auto[0]	3513125	1			T4	64953		T10	43		T20	33
auto[1]	auto[3]	auto[1]	580356	1			T4	6579		T10	6		T20	2
auto[1]	auto[3]	auto[2]	608799	1			T4	6600		T10	4		T20	1
auto[1]	auto[3]	auto[3]	1288516	1			T4	689		T10	1		T18	4