Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	314579554	132742	0	0
ctrl_regwen_rd_A	314579554	7537	0	0
exec_rd_A	314579554	6929	0	0
exec_regwen_rd_A	314579554	7372	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314579554	132742	0	0
T12	226580	5835	0	0
T13	3353	0	0	0
T15	279839	0	0	0
T18	5685	0	0	0
T19	660786	0	0	0
T20	335229	0	0	0
T21	0	3486	0	0
T24	1580	0	0	0
T29	0	3986	0	0
T42	0	672	0	0
T43	0	7231	0	0
T44	0	1732	0	0
T45	0	4627	0	0
T46	0	2993	0	0
T47	0	3840	0	0
T48	0	1411	0	0
T49	8765	0	0	0
T50	6656	0	0	0
T51	41393	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314579554	7537	0	0
T28	257206	0	0	0
T42	20596	205	0	0
T43	198735	0	0	0
T45	0	950	0	0
T74	194520	0	0	0
T95	0	460	0	0
T96	0	413	0	0
T97	0	390	0	0
T98	0	618	0	0
T99	0	104	0	0
T100	0	213	0	0
T101	0	240	0	0
T102	0	634	0	0
T103	297181	0	0	0
T104	137495	0	0	0
T105	4695	0	0	0
T106	119162	0	0	0
T107	110563	0	0	0
T108	11189	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314579554	6929	0	0
T28	257206	0	0	0
T42	20596	134	0	0
T43	198735	0	0	0
T45	0	886	0	0
T74	194520	0	0	0
T95	0	347	0	0
T96	0	383	0	0
T97	0	327	0	0
T98	0	670	0	0
T99	0	69	0	0
T100	0	158	0	0
T101	0	179	0	0
T102	0	699	0	0
T103	297181	0	0	0
T104	137495	0	0	0
T105	4695	0	0	0
T106	119162	0	0	0
T107	110563	0	0	0
T108	11189	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314579554	7372	0	0
T28	257206	0	0	0
T42	20596	135	0	0
T43	198735	0	0	0
T45	0	1008	0	0
T74	194520	0	0	0
T95	0	442	0	0
T96	0	402	0	0
T97	0	310	0	0
T98	0	596	0	0
T99	0	110	0	0
T100	0	217	0	0
T101	0	185	0	0
T102	0	760	0	0
T103	297181	0	0	0
T104	137495	0	0	0
T105	4695	0	0	0
T106	119162	0	0	0
T107	110563	0	0	0
T108	11189	0	0	0