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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.08 99.81 96.99 100.00 100.00 98.57 99.70 98.52


Total test records in report: 1024
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T790 /workspace/coverage/default/35.sram_ctrl_lc_escalation.3711960458 May 12 12:59:33 PM PDT 24 May 12 12:59:41 PM PDT 24 1404557042 ps
T791 /workspace/coverage/default/4.sram_ctrl_alert_test.831609489 May 12 12:58:07 PM PDT 24 May 12 12:58:10 PM PDT 24 36223532 ps
T792 /workspace/coverage/default/15.sram_ctrl_partial_access.193652408 May 12 12:58:49 PM PDT 24 May 12 12:58:57 PM PDT 24 1724922540 ps
T793 /workspace/coverage/default/30.sram_ctrl_partial_access.1129768745 May 12 12:59:10 PM PDT 24 May 12 12:59:19 PM PDT 24 745865336 ps
T794 /workspace/coverage/default/20.sram_ctrl_multiple_keys.2475099435 May 12 12:58:52 PM PDT 24 May 12 01:11:02 PM PDT 24 3133234231 ps
T795 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3019893810 May 12 01:00:20 PM PDT 24 May 12 01:05:25 PM PDT 24 13909845145 ps
T796 /workspace/coverage/default/49.sram_ctrl_executable.4056334896 May 12 01:00:29 PM PDT 24 May 12 01:41:50 PM PDT 24 23317262076 ps
T797 /workspace/coverage/default/42.sram_ctrl_ram_cfg.892860689 May 12 12:59:56 PM PDT 24 May 12 12:59:57 PM PDT 24 84087017 ps
T798 /workspace/coverage/default/9.sram_ctrl_bijection.2029105291 May 12 12:58:35 PM PDT 24 May 12 12:58:57 PM PDT 24 1090471181 ps
T799 /workspace/coverage/default/24.sram_ctrl_lc_escalation.3212550185 May 12 12:59:07 PM PDT 24 May 12 12:59:16 PM PDT 24 1837264245 ps
T800 /workspace/coverage/default/44.sram_ctrl_bijection.3870125341 May 12 01:00:08 PM PDT 24 May 12 01:01:33 PM PDT 24 18393796809 ps
T801 /workspace/coverage/default/32.sram_ctrl_stress_all.1575437876 May 12 12:59:31 PM PDT 24 May 12 01:42:35 PM PDT 24 11013742019 ps
T802 /workspace/coverage/default/21.sram_ctrl_stress_pipeline.2886372410 May 12 12:58:58 PM PDT 24 May 12 01:00:48 PM PDT 24 2338005299 ps
T803 /workspace/coverage/default/26.sram_ctrl_multiple_keys.393872511 May 12 12:59:02 PM PDT 24 May 12 12:59:47 PM PDT 24 1222286306 ps
T804 /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.643633349 May 12 12:58:56 PM PDT 24 May 12 01:00:08 PM PDT 24 24912376731 ps
T805 /workspace/coverage/default/7.sram_ctrl_stress_all.756734153 May 12 12:58:11 PM PDT 24 May 12 01:30:20 PM PDT 24 12860773680 ps
T806 /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3548016303 May 12 12:58:43 PM PDT 24 May 12 12:58:46 PM PDT 24 171841241 ps
T807 /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.756311227 May 12 12:59:10 PM PDT 24 May 12 01:00:17 PM PDT 24 1302460821 ps
T808 /workspace/coverage/default/24.sram_ctrl_regwen.3951606607 May 12 12:59:05 PM PDT 24 May 12 01:06:50 PM PDT 24 14768532478 ps
T809 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.1070429240 May 12 12:59:59 PM PDT 24 May 12 01:05:20 PM PDT 24 14327381017 ps
T810 /workspace/coverage/default/30.sram_ctrl_access_during_key_req.3624634638 May 12 12:59:12 PM PDT 24 May 12 01:08:07 PM PDT 24 1934818178 ps
T811 /workspace/coverage/default/16.sram_ctrl_bijection.3134303692 May 12 12:58:50 PM PDT 24 May 12 12:59:44 PM PDT 24 12272866730 ps
T812 /workspace/coverage/default/15.sram_ctrl_lc_escalation.3585959966 May 12 12:58:53 PM PDT 24 May 12 12:58:57 PM PDT 24 382585332 ps
T813 /workspace/coverage/default/33.sram_ctrl_stress_pipeline.966255386 May 12 12:59:24 PM PDT 24 May 12 01:03:12 PM PDT 24 2344037124 ps
T814 /workspace/coverage/default/38.sram_ctrl_smoke.1629870378 May 12 12:59:38 PM PDT 24 May 12 01:00:31 PM PDT 24 111799194 ps
T815 /workspace/coverage/default/26.sram_ctrl_access_during_key_req.1582551951 May 12 12:59:04 PM PDT 24 May 12 01:16:27 PM PDT 24 12201572044 ps
T816 /workspace/coverage/default/21.sram_ctrl_ram_cfg.1174944997 May 12 12:58:54 PM PDT 24 May 12 12:58:56 PM PDT 24 92021773 ps
T817 /workspace/coverage/default/11.sram_ctrl_alert_test.3277220149 May 12 12:58:23 PM PDT 24 May 12 12:58:24 PM PDT 24 33147751 ps
T818 /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.4161482206 May 12 12:58:38 PM PDT 24 May 12 12:59:12 PM PDT 24 121873754 ps
T819 /workspace/coverage/default/12.sram_ctrl_ram_cfg.2840096420 May 12 12:58:37 PM PDT 24 May 12 12:58:38 PM PDT 24 83335123 ps
T820 /workspace/coverage/default/29.sram_ctrl_stress_pipeline.4157305712 May 12 12:59:03 PM PDT 24 May 12 01:02:57 PM PDT 24 15596922077 ps
T821 /workspace/coverage/default/35.sram_ctrl_smoke.2362415486 May 12 12:59:31 PM PDT 24 May 12 12:59:39 PM PDT 24 189991435 ps
T822 /workspace/coverage/default/23.sram_ctrl_access_during_key_req.169546840 May 12 12:59:00 PM PDT 24 May 12 01:12:14 PM PDT 24 13165132685 ps
T823 /workspace/coverage/default/38.sram_ctrl_regwen.834668559 May 12 12:59:46 PM PDT 24 May 12 01:11:48 PM PDT 24 17757864012 ps
T824 /workspace/coverage/default/30.sram_ctrl_ram_cfg.3340926382 May 12 12:59:10 PM PDT 24 May 12 12:59:12 PM PDT 24 76162356 ps
T825 /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1075542926 May 12 12:58:07 PM PDT 24 May 12 12:58:16 PM PDT 24 220745473 ps
T826 /workspace/coverage/default/38.sram_ctrl_mem_walk.3785702982 May 12 12:59:49 PM PDT 24 May 12 12:59:54 PM PDT 24 226675679 ps
T827 /workspace/coverage/default/13.sram_ctrl_partial_access.2075876059 May 12 12:58:34 PM PDT 24 May 12 12:58:48 PM PDT 24 2727317280 ps
T828 /workspace/coverage/default/39.sram_ctrl_alert_test.4019922663 May 12 12:59:45 PM PDT 24 May 12 12:59:47 PM PDT 24 35020590 ps
T829 /workspace/coverage/default/19.sram_ctrl_lc_escalation.629972227 May 12 12:58:59 PM PDT 24 May 12 12:59:06 PM PDT 24 6942808089 ps
T830 /workspace/coverage/default/2.sram_ctrl_stress_all.1294185650 May 12 12:58:14 PM PDT 24 May 12 01:19:37 PM PDT 24 7761392775 ps
T831 /workspace/coverage/default/0.sram_ctrl_stress_all.3582543013 May 12 12:58:09 PM PDT 24 May 12 01:23:31 PM PDT 24 11015553048 ps
T832 /workspace/coverage/default/29.sram_ctrl_access_during_key_req.382086278 May 12 12:59:03 PM PDT 24 May 12 01:21:16 PM PDT 24 41585083540 ps
T833 /workspace/coverage/default/0.sram_ctrl_access_during_key_req.1721299730 May 12 12:58:08 PM PDT 24 May 12 01:10:32 PM PDT 24 1591233478 ps
T834 /workspace/coverage/default/19.sram_ctrl_alert_test.2233634384 May 12 12:58:59 PM PDT 24 May 12 12:59:00 PM PDT 24 42509457 ps
T835 /workspace/coverage/default/18.sram_ctrl_multiple_keys.4051302434 May 12 12:58:47 PM PDT 24 May 12 01:08:05 PM PDT 24 8171154807 ps
T836 /workspace/coverage/default/37.sram_ctrl_regwen.2795275688 May 12 12:59:41 PM PDT 24 May 12 01:12:44 PM PDT 24 12488864569 ps
T837 /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3741853725 May 12 12:58:08 PM PDT 24 May 12 01:04:27 PM PDT 24 30968364688 ps
T838 /workspace/coverage/default/10.sram_ctrl_executable.4176464397 May 12 12:58:39 PM PDT 24 May 12 01:17:30 PM PDT 24 101022431367 ps
T839 /workspace/coverage/default/0.sram_ctrl_max_throughput.1927221454 May 12 12:58:09 PM PDT 24 May 12 12:59:50 PM PDT 24 499901779 ps
T840 /workspace/coverage/default/19.sram_ctrl_mem_partial_access.2305289178 May 12 12:58:54 PM PDT 24 May 12 12:59:00 PM PDT 24 686288147 ps
T841 /workspace/coverage/default/1.sram_ctrl_smoke.2572162311 May 12 12:58:04 PM PDT 24 May 12 12:58:14 PM PDT 24 290039648 ps
T842 /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.2713298395 May 12 12:58:06 PM PDT 24 May 12 12:58:51 PM PDT 24 539451407 ps
T843 /workspace/coverage/default/31.sram_ctrl_alert_test.3980303184 May 12 12:59:19 PM PDT 24 May 12 12:59:20 PM PDT 24 16872004 ps
T844 /workspace/coverage/default/30.sram_ctrl_executable.338384365 May 12 12:59:12 PM PDT 24 May 12 01:02:15 PM PDT 24 13399455529 ps
T845 /workspace/coverage/default/31.sram_ctrl_mem_walk.1182558848 May 12 12:59:19 PM PDT 24 May 12 12:59:24 PM PDT 24 250684313 ps
T846 /workspace/coverage/default/6.sram_ctrl_lc_escalation.3627104156 May 12 12:58:35 PM PDT 24 May 12 12:58:41 PM PDT 24 430263798 ps
T847 /workspace/coverage/default/24.sram_ctrl_stress_pipeline.2667677130 May 12 12:59:00 PM PDT 24 May 12 01:03:48 PM PDT 24 6325838024 ps
T848 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.95734575 May 12 12:59:05 PM PDT 24 May 12 12:59:12 PM PDT 24 667691772 ps
T849 /workspace/coverage/default/40.sram_ctrl_max_throughput.3390226692 May 12 12:59:52 PM PDT 24 May 12 12:59:57 PM PDT 24 199891073 ps
T850 /workspace/coverage/default/31.sram_ctrl_bijection.1683436221 May 12 12:59:25 PM PDT 24 May 12 12:59:56 PM PDT 24 1461269879 ps
T851 /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.117400740 May 12 12:59:11 PM PDT 24 May 12 12:59:21 PM PDT 24 74838814 ps
T852 /workspace/coverage/default/6.sram_ctrl_stress_all.1442436336 May 12 12:58:30 PM PDT 24 May 12 01:01:49 PM PDT 24 7891961117 ps
T853 /workspace/coverage/default/12.sram_ctrl_stress_all.1409503095 May 12 12:58:41 PM PDT 24 May 12 01:08:14 PM PDT 24 47583473868 ps
T854 /workspace/coverage/default/14.sram_ctrl_lc_escalation.1164865836 May 12 12:58:36 PM PDT 24 May 12 12:58:43 PM PDT 24 1210968784 ps
T855 /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.907758997 May 12 01:00:21 PM PDT 24 May 12 01:07:58 PM PDT 24 73327459451 ps
T856 /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2728373258 May 12 12:59:58 PM PDT 24 May 12 01:00:34 PM PDT 24 1426983480 ps
T857 /workspace/coverage/default/44.sram_ctrl_multiple_keys.1871177980 May 12 01:00:09 PM PDT 24 May 12 01:25:22 PM PDT 24 76956878764 ps
T858 /workspace/coverage/default/2.sram_ctrl_access_during_key_req.2320314 May 12 12:58:17 PM PDT 24 May 12 01:14:04 PM PDT 24 3185924196 ps
T859 /workspace/coverage/default/45.sram_ctrl_ram_cfg.810672226 May 12 01:00:14 PM PDT 24 May 12 01:00:16 PM PDT 24 31239827 ps
T860 /workspace/coverage/default/2.sram_ctrl_multiple_keys.2841390660 May 12 12:58:16 PM PDT 24 May 12 01:15:36 PM PDT 24 21095220344 ps
T861 /workspace/coverage/default/39.sram_ctrl_partial_access.2569384232 May 12 12:59:45 PM PDT 24 May 12 01:00:41 PM PDT 24 1043260194 ps
T862 /workspace/coverage/default/24.sram_ctrl_executable.406215194 May 12 12:59:02 PM PDT 24 May 12 01:15:00 PM PDT 24 11021410115 ps
T863 /workspace/coverage/default/18.sram_ctrl_alert_test.3661608087 May 12 12:58:52 PM PDT 24 May 12 12:58:53 PM PDT 24 23470840 ps
T864 /workspace/coverage/default/29.sram_ctrl_multiple_keys.1384195589 May 12 12:59:03 PM PDT 24 May 12 01:10:42 PM PDT 24 97723124130 ps
T865 /workspace/coverage/default/7.sram_ctrl_lc_escalation.2454462779 May 12 12:58:22 PM PDT 24 May 12 12:58:28 PM PDT 24 419561114 ps
T866 /workspace/coverage/default/32.sram_ctrl_access_during_key_req.162182729 May 12 12:59:35 PM PDT 24 May 12 01:19:14 PM PDT 24 3709753371 ps
T867 /workspace/coverage/default/2.sram_ctrl_mem_walk.2792034476 May 12 12:58:18 PM PDT 24 May 12 12:58:27 PM PDT 24 258735923 ps
T868 /workspace/coverage/default/6.sram_ctrl_alert_test.3031844869 May 12 12:58:50 PM PDT 24 May 12 12:58:51 PM PDT 24 15163253 ps
T869 /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2556718976 May 12 12:58:21 PM PDT 24 May 12 01:03:58 PM PDT 24 1765535950 ps
T870 /workspace/coverage/default/10.sram_ctrl_regwen.1270401553 May 12 12:58:49 PM PDT 24 May 12 12:59:22 PM PDT 24 2075743415 ps
T871 /workspace/coverage/default/42.sram_ctrl_lc_escalation.2529397566 May 12 12:59:56 PM PDT 24 May 12 01:00:05 PM PDT 24 860375901 ps
T872 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3945364688 May 12 12:59:20 PM PDT 24 May 12 01:00:46 PM PDT 24 456253590 ps
T873 /workspace/coverage/default/41.sram_ctrl_lc_escalation.1577460349 May 12 12:59:53 PM PDT 24 May 12 12:59:55 PM PDT 24 117156169 ps
T874 /workspace/coverage/default/33.sram_ctrl_lc_escalation.2692405832 May 12 12:59:25 PM PDT 24 May 12 12:59:32 PM PDT 24 614707097 ps
T875 /workspace/coverage/default/12.sram_ctrl_mem_partial_access.692239620 May 12 12:58:40 PM PDT 24 May 12 12:58:45 PM PDT 24 833613972 ps
T876 /workspace/coverage/default/49.sram_ctrl_stress_pipeline.748374559 May 12 01:00:30 PM PDT 24 May 12 01:03:42 PM PDT 24 8569347173 ps
T877 /workspace/coverage/default/25.sram_ctrl_regwen.1121871372 May 12 12:59:05 PM PDT 24 May 12 01:17:59 PM PDT 24 45909594952 ps
T878 /workspace/coverage/default/6.sram_ctrl_ram_cfg.278359303 May 12 12:58:09 PM PDT 24 May 12 12:58:13 PM PDT 24 42442971 ps
T879 /workspace/coverage/default/19.sram_ctrl_max_throughput.492130783 May 12 12:58:56 PM PDT 24 May 12 01:00:32 PM PDT 24 1597403089 ps
T880 /workspace/coverage/default/9.sram_ctrl_smoke.1404089214 May 12 12:58:21 PM PDT 24 May 12 12:59:58 PM PDT 24 685752072 ps
T881 /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.724317714 May 12 12:59:30 PM PDT 24 May 12 01:08:28 PM PDT 24 22329399935 ps
T882 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.3801415747 May 12 12:59:32 PM PDT 24 May 12 01:14:30 PM PDT 24 7297162903 ps
T883 /workspace/coverage/default/25.sram_ctrl_stress_pipeline.2188354169 May 12 12:59:01 PM PDT 24 May 12 01:02:07 PM PDT 24 9782921712 ps
T884 /workspace/coverage/default/14.sram_ctrl_stress_all.3862918608 May 12 12:58:44 PM PDT 24 May 12 01:57:18 PM PDT 24 51324363449 ps
T885 /workspace/coverage/default/0.sram_ctrl_smoke.1493650784 May 12 12:58:13 PM PDT 24 May 12 12:58:16 PM PDT 24 39826343 ps
T886 /workspace/coverage/default/28.sram_ctrl_partial_access.2351229930 May 12 12:59:07 PM PDT 24 May 12 01:01:58 PM PDT 24 642054281 ps
T887 /workspace/coverage/default/48.sram_ctrl_mem_walk.482545201 May 12 01:00:30 PM PDT 24 May 12 01:00:35 PM PDT 24 3715468261 ps
T888 /workspace/coverage/default/35.sram_ctrl_ram_cfg.2274247376 May 12 12:59:35 PM PDT 24 May 12 12:59:37 PM PDT 24 28885342 ps
T889 /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.872807045 May 12 12:59:09 PM PDT 24 May 12 12:59:13 PM PDT 24 84685354 ps
T890 /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1276354350 May 12 12:58:56 PM PDT 24 May 12 01:01:56 PM PDT 24 13070312956 ps
T891 /workspace/coverage/default/49.sram_ctrl_max_throughput.4186734822 May 12 01:00:32 PM PDT 24 May 12 01:00:33 PM PDT 24 208472910 ps
T892 /workspace/coverage/default/17.sram_ctrl_access_during_key_req.2442333684 May 12 12:58:46 PM PDT 24 May 12 01:26:58 PM PDT 24 9125159332 ps
T893 /workspace/coverage/default/36.sram_ctrl_lc_escalation.1347281302 May 12 12:59:35 PM PDT 24 May 12 12:59:41 PM PDT 24 866560189 ps
T894 /workspace/coverage/default/38.sram_ctrl_partial_access.2832875092 May 12 12:59:43 PM PDT 24 May 12 01:01:36 PM PDT 24 210355886 ps
T895 /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1714084206 May 12 12:58:57 PM PDT 24 May 12 01:02:39 PM PDT 24 9223448318 ps
T896 /workspace/coverage/default/4.sram_ctrl_access_during_key_req.4145659511 May 12 12:58:09 PM PDT 24 May 12 01:09:14 PM PDT 24 5737679048 ps
T897 /workspace/coverage/default/7.sram_ctrl_smoke.2180626300 May 12 12:58:13 PM PDT 24 May 12 12:58:19 PM PDT 24 2973576289 ps
T898 /workspace/coverage/default/10.sram_ctrl_max_throughput.1792620066 May 12 12:58:48 PM PDT 24 May 12 01:00:36 PM PDT 24 260856313 ps
T899 /workspace/coverage/default/9.sram_ctrl_access_during_key_req.3051686312 May 12 12:58:43 PM PDT 24 May 12 01:06:43 PM PDT 24 7298150614 ps
T900 /workspace/coverage/default/47.sram_ctrl_mem_walk.2478539529 May 12 01:00:26 PM PDT 24 May 12 01:00:31 PM PDT 24 800210542 ps
T901 /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1753874976 May 12 12:59:50 PM PDT 24 May 12 01:01:22 PM PDT 24 358792445 ps
T902 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2107631986 May 12 01:00:14 PM PDT 24 May 12 01:03:11 PM PDT 24 6691278260 ps
T903 /workspace/coverage/default/14.sram_ctrl_mem_walk.312863655 May 12 12:58:54 PM PDT 24 May 12 12:59:05 PM PDT 24 2100618549 ps
T904 /workspace/coverage/default/37.sram_ctrl_smoke.2133870778 May 12 12:59:40 PM PDT 24 May 12 12:59:57 PM PDT 24 932131303 ps
T905 /workspace/coverage/default/1.sram_ctrl_bijection.345869405 May 12 12:58:08 PM PDT 24 May 12 12:59:00 PM PDT 24 4016587070 ps
T906 /workspace/coverage/default/38.sram_ctrl_ram_cfg.1018039904 May 12 12:59:46 PM PDT 24 May 12 12:59:47 PM PDT 24 71582121 ps
T907 /workspace/coverage/default/15.sram_ctrl_bijection.2400160068 May 12 12:58:57 PM PDT 24 May 12 12:59:32 PM PDT 24 2199903095 ps
T908 /workspace/coverage/default/20.sram_ctrl_lc_escalation.1648572120 May 12 12:58:51 PM PDT 24 May 12 12:58:56 PM PDT 24 782664564 ps
T909 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.888841250 May 12 12:58:19 PM PDT 24 May 12 01:01:23 PM PDT 24 4253319607 ps
T910 /workspace/coverage/default/47.sram_ctrl_alert_test.4163821592 May 12 01:00:26 PM PDT 24 May 12 01:00:26 PM PDT 24 14191693 ps
T911 /workspace/coverage/default/18.sram_ctrl_smoke.2727733754 May 12 12:58:57 PM PDT 24 May 12 12:59:05 PM PDT 24 232066297 ps
T912 /workspace/coverage/default/21.sram_ctrl_stress_all.2111304155 May 12 12:59:01 PM PDT 24 May 12 01:16:25 PM PDT 24 138765931900 ps
T913 /workspace/coverage/default/49.sram_ctrl_mem_partial_access.3145157921 May 12 01:00:34 PM PDT 24 May 12 01:00:38 PM PDT 24 117413619 ps
T914 /workspace/coverage/default/34.sram_ctrl_ram_cfg.3313645242 May 12 12:59:27 PM PDT 24 May 12 12:59:28 PM PDT 24 31680369 ps
T915 /workspace/coverage/default/17.sram_ctrl_smoke.1342275698 May 12 12:58:36 PM PDT 24 May 12 12:58:44 PM PDT 24 181939178 ps
T916 /workspace/coverage/default/38.sram_ctrl_alert_test.2794505246 May 12 12:59:49 PM PDT 24 May 12 12:59:50 PM PDT 24 13141144 ps
T917 /workspace/coverage/default/37.sram_ctrl_max_throughput.2850985996 May 12 12:59:40 PM PDT 24 May 12 12:59:59 PM PDT 24 78693679 ps
T918 /workspace/coverage/default/31.sram_ctrl_partial_access.1496552151 May 12 12:59:13 PM PDT 24 May 12 12:59:28 PM PDT 24 868357363 ps
T919 /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2181242076 May 12 12:59:43 PM PDT 24 May 12 01:02:49 PM PDT 24 12028516137 ps
T920 /workspace/coverage/default/29.sram_ctrl_bijection.1336605118 May 12 12:59:02 PM PDT 24 May 12 01:00:16 PM PDT 24 7102939999 ps
T921 /workspace/coverage/default/4.sram_ctrl_lc_escalation.102355331 May 12 12:58:09 PM PDT 24 May 12 12:58:20 PM PDT 24 1236779447 ps
T922 /workspace/coverage/default/44.sram_ctrl_mem_partial_access.540626951 May 12 01:00:09 PM PDT 24 May 12 01:00:15 PM PDT 24 303017412 ps
T923 /workspace/coverage/default/49.sram_ctrl_alert_test.2762364364 May 12 01:00:42 PM PDT 24 May 12 01:00:43 PM PDT 24 15378959 ps
T924 /workspace/coverage/default/21.sram_ctrl_partial_access.2239477561 May 12 12:58:59 PM PDT 24 May 12 12:59:04 PM PDT 24 195641293 ps
T925 /workspace/coverage/default/18.sram_ctrl_stress_all.1441493377 May 12 12:58:52 PM PDT 24 May 12 01:31:31 PM PDT 24 7573600005 ps
T926 /workspace/coverage/default/32.sram_ctrl_smoke.731280034 May 12 12:59:24 PM PDT 24 May 12 12:59:27 PM PDT 24 65401447 ps
T927 /workspace/coverage/default/8.sram_ctrl_stress_pipeline.3039380325 May 12 12:58:42 PM PDT 24 May 12 01:02:30 PM PDT 24 2468165712 ps
T928 /workspace/coverage/default/23.sram_ctrl_alert_test.1132576816 May 12 12:59:09 PM PDT 24 May 12 12:59:11 PM PDT 24 32989256 ps
T929 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1758577034 May 12 12:59:05 PM PDT 24 May 12 01:01:57 PM PDT 24 13295523316 ps
T54 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3962528631 May 12 12:49:24 PM PDT 24 May 12 12:49:25 PM PDT 24 24295521 ps
T92 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.645015439 May 12 12:49:19 PM PDT 24 May 12 12:49:21 PM PDT 24 88291334 ps
T55 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3545915393 May 12 12:49:29 PM PDT 24 May 12 12:49:34 PM PDT 24 813481641 ps
T56 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3523634473 May 12 12:49:11 PM PDT 24 May 12 12:49:13 PM PDT 24 17446783 ps
T57 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1031333326 May 12 12:49:24 PM PDT 24 May 12 12:49:27 PM PDT 24 1362300917 ps
T930 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3628505888 May 12 12:49:20 PM PDT 24 May 12 12:49:23 PM PDT 24 363163361 ps
T58 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.4159289863 May 12 12:49:30 PM PDT 24 May 12 12:49:33 PM PDT 24 230723755 ps
T931 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3529144600 May 12 12:49:18 PM PDT 24 May 12 12:49:20 PM PDT 24 34024536 ps
T93 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1379321791 May 12 12:49:16 PM PDT 24 May 12 12:49:19 PM PDT 24 1062798000 ps
T932 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3616205325 May 12 12:49:19 PM PDT 24 May 12 12:49:21 PM PDT 24 114158592 ps
T91 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2327004409 May 12 12:49:21 PM PDT 24 May 12 12:49:22 PM PDT 24 42602961 ps
T59 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.131746727 May 12 12:49:35 PM PDT 24 May 12 12:49:36 PM PDT 24 54602243 ps
T60 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3223099742 May 12 12:49:26 PM PDT 24 May 12 12:49:28 PM PDT 24 42790961 ps
T933 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.767766588 May 12 12:49:34 PM PDT 24 May 12 12:49:37 PM PDT 24 132742812 ps
T61 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3171730348 May 12 12:49:28 PM PDT 24 May 12 12:49:30 PM PDT 24 41679539 ps
T94 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1398966552 May 12 12:49:30 PM PDT 24 May 12 12:49:38 PM PDT 24 313895230 ps
T934 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1863275632 May 12 12:49:27 PM PDT 24 May 12 12:49:30 PM PDT 24 45218432 ps
T62 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3645580419 May 12 12:49:24 PM PDT 24 May 12 12:49:25 PM PDT 24 31787121 ps
T114 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4219193571 May 12 12:49:28 PM PDT 24 May 12 12:49:36 PM PDT 24 507880360 ps
T109 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1092461714 May 12 12:49:24 PM PDT 24 May 12 12:49:27 PM PDT 24 214253967 ps
T935 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2691304086 May 12 12:49:20 PM PDT 24 May 12 12:49:22 PM PDT 24 104995144 ps
T86 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2634658568 May 12 12:49:24 PM PDT 24 May 12 12:49:25 PM PDT 24 41052852 ps
T63 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.862287650 May 12 12:49:32 PM PDT 24 May 12 12:49:34 PM PDT 24 28636358 ps
T65 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1626835103 May 12 12:49:27 PM PDT 24 May 12 12:49:28 PM PDT 24 44100401 ps
T936 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.552700037 May 12 12:49:28 PM PDT 24 May 12 12:49:30 PM PDT 24 16856974 ps
T937 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2345599974 May 12 12:49:20 PM PDT 24 May 12 12:49:22 PM PDT 24 69138947 ps
T938 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1546466230 May 12 12:49:30 PM PDT 24 May 12 12:49:32 PM PDT 24 20488294 ps
T939 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3133521595 May 12 12:49:29 PM PDT 24 May 12 12:49:32 PM PDT 24 41301569 ps
T110 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1191539636 May 12 12:49:25 PM PDT 24 May 12 12:49:28 PM PDT 24 1338960434 ps
T111 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.856154150 May 12 12:49:31 PM PDT 24 May 12 12:49:35 PM PDT 24 182950609 ps
T940 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3486432669 May 12 12:49:16 PM PDT 24 May 12 12:49:18 PM PDT 24 61087534 ps
T66 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2989905380 May 12 12:49:22 PM PDT 24 May 12 12:49:26 PM PDT 24 480036112 ps
T112 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2353657635 May 12 12:49:33 PM PDT 24 May 12 12:49:36 PM PDT 24 299708841 ps
T941 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1424190821 May 12 12:49:25 PM PDT 24 May 12 12:49:29 PM PDT 24 80607066 ps
T942 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1754132664 May 12 12:49:24 PM PDT 24 May 12 12:49:27 PM PDT 24 334837574 ps
T943 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3553154044 May 12 12:49:11 PM PDT 24 May 12 12:49:13 PM PDT 24 56428517 ps
T67 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.568169675 May 12 12:49:27 PM PDT 24 May 12 12:49:32 PM PDT 24 1609504221 ps
T944 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2905084673 May 12 12:49:15 PM PDT 24 May 12 12:49:16 PM PDT 24 29068614 ps
T77 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3826872517 May 12 12:49:18 PM PDT 24 May 12 12:49:20 PM PDT 24 23029831 ps
T945 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1609952884 May 12 12:49:16 PM PDT 24 May 12 12:49:17 PM PDT 24 16592216 ps
T946 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1917018000 May 12 12:49:29 PM PDT 24 May 12 12:49:31 PM PDT 24 19699754 ps
T68 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.46700093 May 12 12:49:12 PM PDT 24 May 12 12:49:14 PM PDT 24 16122779 ps
T947 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4160038720 May 12 12:49:36 PM PDT 24 May 12 12:49:38 PM PDT 24 180603802 ps
T948 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1684125332 May 12 12:49:26 PM PDT 24 May 12 12:49:27 PM PDT 24 38265070 ps
T949 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3814687056 May 12 12:49:20 PM PDT 24 May 12 12:49:23 PM PDT 24 1833252935 ps
T950 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3599169937 May 12 12:49:19 PM PDT 24 May 12 12:49:21 PM PDT 24 17500309 ps
T951 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3317608059 May 12 12:49:18 PM PDT 24 May 12 12:49:19 PM PDT 24 18519823 ps
T952 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3829382425 May 12 12:49:10 PM PDT 24 May 12 12:49:12 PM PDT 24 22576365 ps
T953 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1078843850 May 12 12:49:31 PM PDT 24 May 12 12:49:33 PM PDT 24 79758535 ps
T954 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2371920486 May 12 12:49:16 PM PDT 24 May 12 12:49:18 PM PDT 24 106170861 ps
T955 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.4236970711 May 12 12:49:30 PM PDT 24 May 12 12:49:32 PM PDT 24 27977334 ps
T956 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3885344251 May 12 12:49:21 PM PDT 24 May 12 12:49:25 PM PDT 24 38543932 ps
T957 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2186947004 May 12 12:49:28 PM PDT 24 May 12 12:49:30 PM PDT 24 56033341 ps
T958 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3239440114 May 12 12:49:18 PM PDT 24 May 12 12:49:20 PM PDT 24 16567604 ps
T117 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2932523230 May 12 12:49:21 PM PDT 24 May 12 12:49:24 PM PDT 24 1428361674 ps
T959 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.386506898 May 12 12:49:31 PM PDT 24 May 12 12:49:33 PM PDT 24 55735651 ps
T960 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1254577643 May 12 12:49:11 PM PDT 24 May 12 12:49:16 PM PDT 24 149651719 ps
T961 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2994498692 May 12 12:49:37 PM PDT 24 May 12 12:49:41 PM PDT 24 147825301 ps
T962 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.901699609 May 12 12:49:27 PM PDT 24 May 12 12:49:29 PM PDT 24 78992279 ps
T963 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2736651470 May 12 12:49:25 PM PDT 24 May 12 12:49:27 PM PDT 24 92409582 ps
T118 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2480858453 May 12 12:49:26 PM PDT 24 May 12 12:49:28 PM PDT 24 271189521 ps
T113 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4268437747 May 12 12:49:26 PM PDT 24 May 12 12:49:30 PM PDT 24 621152169 ps
T115 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3573639505 May 12 12:49:23 PM PDT 24 May 12 12:49:26 PM PDT 24 246258411 ps
T964 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3370793940 May 12 12:49:13 PM PDT 24 May 12 12:49:14 PM PDT 24 60499000 ps
T78 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1659696261 May 12 12:49:29 PM PDT 24 May 12 12:49:31 PM PDT 24 65928370 ps
T965 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3848638518 May 12 12:49:33 PM PDT 24 May 12 12:49:35 PM PDT 24 156947125 ps
T119 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2629431792 May 12 12:49:23 PM PDT 24 May 12 12:49:26 PM PDT 24 257867706 ps
T966 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1359756465 May 12 12:49:16 PM PDT 24 May 12 12:49:21 PM PDT 24 109224940 ps
T967 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.581513997 May 12 12:49:21 PM PDT 24 May 12 12:49:23 PM PDT 24 288647028 ps
T968 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.989938941 May 12 12:49:30 PM PDT 24 May 12 12:49:32 PM PDT 24 20554203 ps
T969 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.4106087114 May 12 12:49:35 PM PDT 24 May 12 12:49:36 PM PDT 24 18324192 ps
T970 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1329672687 May 12 12:49:30 PM PDT 24 May 12 12:49:32 PM PDT 24 23718761 ps
T971 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1234718773 May 12 12:49:29 PM PDT 24 May 12 12:49:35 PM PDT 24 5471675582 ps
T972 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.397122476 May 12 12:49:17 PM PDT 24 May 12 12:49:20 PM PDT 24 476378193 ps
T973 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2622536464 May 12 12:49:29 PM PDT 24 May 12 12:49:33 PM PDT 24 45410124 ps
T974 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2900772844 May 12 12:49:28 PM PDT 24 May 12 12:49:30 PM PDT 24 23240465 ps
T975 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1372968447 May 12 12:49:29 PM PDT 24 May 12 12:49:31 PM PDT 24 29275040 ps
T976 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.708359927 May 12 12:49:28 PM PDT 24 May 12 12:49:31 PM PDT 24 74023869 ps
T977 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3419307214 May 12 12:49:25 PM PDT 24 May 12 12:49:27 PM PDT 24 18533716 ps
T978 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3645607060 May 12 12:49:28 PM PDT 24 May 12 12:49:30 PM PDT 24 19634726 ps
T979 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3046039328 May 12 12:49:30 PM PDT 24 May 12 12:49:37 PM PDT 24 178477663 ps
T84 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3440648517 May 12 12:49:24 PM PDT 24 May 12 12:49:26 PM PDT 24 22255049 ps
T980 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1336152275 May 12 12:49:20 PM PDT 24 May 12 12:49:23 PM PDT 24 815256806 ps
T981 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1453327059 May 12 12:49:17 PM PDT 24 May 12 12:49:18 PM PDT 24 125220746 ps
T85 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.4074895734 May 12 12:49:23 PM PDT 24 May 12 12:49:27 PM PDT 24 842383050 ps
T982 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2590796561 May 12 12:49:32 PM PDT 24 May 12 12:49:36 PM PDT 24 89908757 ps
T983 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.308921798 May 12 12:49:24 PM PDT 24 May 12 12:49:28 PM PDT 24 87610381 ps
T984 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1328162610 May 12 12:49:27 PM PDT 24 May 12 12:49:28 PM PDT 24 39517970 ps
T79 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2495150551 May 12 12:49:32 PM PDT 24 May 12 12:49:35 PM PDT 24 813937160 ps
T985 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3440381451 May 12 12:49:15 PM PDT 24 May 12 12:49:17 PM PDT 24 162825626 ps
T986 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1613457158 May 12 12:49:27 PM PDT 24 May 12 12:49:30 PM PDT 24 55150063 ps
T987 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3813514905 May 12 12:49:12 PM PDT 24 May 12 12:49:13 PM PDT 24 13085399 ps
T80 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2695795793 May 12 12:49:18 PM PDT 24 May 12 12:49:21 PM PDT 24 1284287806 ps
T988 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.24524995 May 12 12:49:32 PM PDT 24 May 12 12:49:36 PM PDT 24 415937289 ps
T989 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2318794027 May 12 12:49:30 PM PDT 24 May 12 12:49:32 PM PDT 24 20827179 ps
T990 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2877663205 May 12 12:49:29 PM PDT 24 May 12 12:49:33 PM PDT 24 319040119 ps
T991 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.435124382 May 12 12:49:17 PM PDT 24 May 12 12:49:19 PM PDT 24 30361775 ps
T992 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1665761442 May 12 12:49:13 PM PDT 24 May 12 12:49:14 PM PDT 24 76243733 ps
T993 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.224642152 May 12 12:49:22 PM PDT 24 May 12 12:49:23 PM PDT 24 42786411 ps
T994 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3063410544 May 12 12:49:27 PM PDT 24 May 12 12:49:28 PM PDT 24 31602339 ps
T995 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1259137994 May 12 12:49:29 PM PDT 24 May 12 12:49:32 PM PDT 24 32631693 ps
T81 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3071911639 May 12 12:49:24 PM PDT 24 May 12 12:49:29 PM PDT 24 498018233 ps
T996 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3653451121 May 12 12:49:12 PM PDT 24 May 12 12:49:15 PM PDT 24 129140082 ps
T82 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1043856093 May 12 12:49:20 PM PDT 24 May 12 12:49:23 PM PDT 24 836365412 ps
T997 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3486150082 May 12 12:49:11 PM PDT 24 May 12 12:49:14 PM PDT 24 214309484 ps
T998 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1587776840 May 12 12:49:24 PM PDT 24 May 12 12:49:25 PM PDT 24 41164030 ps
T999 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4153410861 May 12 12:49:24 PM PDT 24 May 12 12:49:29 PM PDT 24 456988434 ps
T83 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2517185576 May 12 12:49:32 PM PDT 24 May 12 12:49:34 PM PDT 24 15111591 ps
T1000 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3547150035 May 12 12:49:25 PM PDT 24 May 12 12:49:27 PM PDT 24 125534960 ps
T1001 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1666284647 May 12 12:49:31 PM PDT 24 May 12 12:49:36 PM PDT 24 1562887762 ps
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