Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	144162690	1			T2	249332		T3	14984		T4	1760
instr_valid_dis	107869057	1			T2	249332		T3	14984		T4	1760
instr_en	24977322	1			T6	161022		T7	920660		T57	20982

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10597061	1			T6	148946		T7	68654		T57	20026
sram_ifetch_valid_disable	113513373	1			T2	249332		T3	14984		T4	1760
sram_ifetch_enable	20052256	1			T6	220412		T7	795672		T16	172

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	144162690	1			T2	249332		T3	14984		T4	1760
hw_debug_en_valid_off	113655172	1			T2	249332		T3	14984		T4	1760
hw_debug_en_on	21150666	1			T6	162086		T7	603526		T25	71072

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	113513373	1			T2	249332		T3	14984		T4	1760
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	98672576	1			T2	249332		T3	14984		T4	1760
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9440161	1			T6	28248		T7	131428		T57	20982
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4274809	1			T6	130580		T7	25874		T43	79732
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1255506	1			T58	98916		T133	9566		T129	24262
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2115439	1			T6	114408		T7	25874		T43	79732
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4677668	1			T6	18366		T7	42780		T57	20026
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1348784	1			T57	20026		T43	7336		T58	19816
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2444822	1			T6	18366		T7	42780		T59	46038
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8416857	1			T6	108642		T7	79488		T25	9652
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2993801	1			T6	13802		T25	9652		T43	6428
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4105760	1			T6	7678		T7	74350		T57	20982

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10025110	1			T7	720578		T43	19054		T44	64510
lc_exec_en	8056141	1			T6	35078		T7	481258		T25	61420
valid_exec_dis	107458075	1			T2	249332		T3	14984		T4	1760
invalid_exec_dis	30649317	1			T6	369358		T7	864326		T16	172