Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	43769901	1			T2	113304		T3	7492		T4	788
triple_byte_access	2508672	1			T2	2220		T4	15		T5	142
halfword_access	3761534	1			T2	3364		T4	31		T5	217
byte_access	5024017	1			T2	4635		T4	39		T5	365
zero_access	1264511	1			T2	1143		T4	7		T5	189

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28110896

1

T2

62057

T3

3742

T4

442

auto[1]

28217739

1

T2

62609

T3

3750

T4

438

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21834834	1			T2	56260		T3	3742		T4	398
auto[0]	triple_byte_access	1250910	1			T2	1152		T4	7		T5	14
auto[0]	halfword_access	1877817	1			T2	1685		T4	13		T5	60
auto[0]	byte_access	2510333	1			T2	2345		T4	21		T5	153
auto[0]	zero_access	637002	1			T2	615		T4	3		T5	136
auto[1]	word_access	21935067	1			T2	57044		T3	3750		T4	390
auto[1]	triple_byte_access	1257762	1			T2	1068		T4	8		T5	128
auto[1]	halfword_access	1883717	1			T2	1679		T4	18		T5	157
auto[1]	byte_access	2513684	1			T2	2290		T4	18		T5	212
auto[1]	zero_access	627509	1			T2	528		T4	4		T5	53