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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.08 99.81 96.99 100.00 100.00 98.57 99.70 98.52


Total test records in report: 1028
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T792 /workspace/coverage/default/0.sram_ctrl_smoke.363607273 May 14 02:28:17 PM PDT 24 May 14 02:28:23 PM PDT 24 631620246 ps
T793 /workspace/coverage/default/41.sram_ctrl_partial_access.3699427395 May 14 02:50:58 PM PDT 24 May 14 02:52:53 PM PDT 24 526216630 ps
T794 /workspace/coverage/default/7.sram_ctrl_smoke.1098578626 May 14 02:30:02 PM PDT 24 May 14 02:30:14 PM PDT 24 2739413828 ps
T795 /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.121882103 May 14 02:50:29 PM PDT 24 May 14 02:53:00 PM PDT 24 733909091 ps
T796 /workspace/coverage/default/22.sram_ctrl_regwen.2341889139 May 14 02:41:44 PM PDT 24 May 14 02:53:04 PM PDT 24 6029276157 ps
T797 /workspace/coverage/default/38.sram_ctrl_max_throughput.1411506580 May 14 02:48:59 PM PDT 24 May 14 02:49:11 PM PDT 24 239008733 ps
T798 /workspace/coverage/default/33.sram_ctrl_max_throughput.3522200484 May 14 02:45:42 PM PDT 24 May 14 02:45:45 PM PDT 24 53140442 ps
T799 /workspace/coverage/default/23.sram_ctrl_max_throughput.4187749028 May 14 02:42:09 PM PDT 24 May 14 02:42:12 PM PDT 24 43585808 ps
T800 /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.308349616 May 14 02:47:39 PM PDT 24 May 14 02:55:24 PM PDT 24 83584900276 ps
T801 /workspace/coverage/default/35.sram_ctrl_executable.281628624 May 14 02:47:22 PM PDT 24 May 14 02:49:50 PM PDT 24 1261506439 ps
T802 /workspace/coverage/default/17.sram_ctrl_mem_partial_access.868776250 May 14 02:34:42 PM PDT 24 May 14 02:34:48 PM PDT 24 166412187 ps
T803 /workspace/coverage/default/31.sram_ctrl_regwen.2634441489 May 14 02:44:38 PM PDT 24 May 14 02:59:58 PM PDT 24 2419175147 ps
T804 /workspace/coverage/default/14.sram_ctrl_access_during_key_req.2994740596 May 14 02:33:05 PM PDT 24 May 14 02:51:31 PM PDT 24 2680508275 ps
T805 /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1961259604 May 14 02:28:45 PM PDT 24 May 14 02:30:48 PM PDT 24 277055594 ps
T806 /workspace/coverage/default/21.sram_ctrl_bijection.2702639219 May 14 02:36:02 PM PDT 24 May 14 02:37:16 PM PDT 24 60822993963 ps
T807 /workspace/coverage/default/11.sram_ctrl_regwen.3882684873 May 14 02:31:57 PM PDT 24 May 14 02:32:17 PM PDT 24 515262009 ps
T808 /workspace/coverage/default/3.sram_ctrl_multiple_keys.1991409641 May 14 02:28:46 PM PDT 24 May 14 02:34:39 PM PDT 24 1638488227 ps
T809 /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.677930092 May 14 02:55:04 PM PDT 24 May 14 02:56:48 PM PDT 24 788190619 ps
T810 /workspace/coverage/default/30.sram_ctrl_mem_walk.3810251314 May 14 02:44:15 PM PDT 24 May 14 02:44:22 PM PDT 24 516349323 ps
T811 /workspace/coverage/default/7.sram_ctrl_mem_walk.1730560223 May 14 02:30:12 PM PDT 24 May 14 02:30:21 PM PDT 24 521391999 ps
T812 /workspace/coverage/default/3.sram_ctrl_max_throughput.698037779 May 14 02:28:46 PM PDT 24 May 14 02:29:35 PM PDT 24 361471632 ps
T813 /workspace/coverage/default/7.sram_ctrl_alert_test.2852000758 May 14 02:30:23 PM PDT 24 May 14 02:30:25 PM PDT 24 12994183 ps
T814 /workspace/coverage/default/21.sram_ctrl_regwen.775848426 May 14 02:41:44 PM PDT 24 May 14 03:05:42 PM PDT 24 55760199242 ps
T815 /workspace/coverage/default/2.sram_ctrl_alert_test.2088309036 May 14 02:28:38 PM PDT 24 May 14 02:28:43 PM PDT 24 13261853 ps
T816 /workspace/coverage/default/48.sram_ctrl_multiple_keys.3171912490 May 14 02:55:27 PM PDT 24 May 14 03:04:34 PM PDT 24 78800541077 ps
T817 /workspace/coverage/default/35.sram_ctrl_alert_test.926927449 May 14 02:47:29 PM PDT 24 May 14 02:47:32 PM PDT 24 16130996 ps
T818 /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3338834705 May 14 02:46:32 PM PDT 24 May 14 02:49:31 PM PDT 24 1347711134 ps
T819 /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2680115398 May 14 02:29:39 PM PDT 24 May 14 02:30:42 PM PDT 24 1628752985 ps
T820 /workspace/coverage/default/26.sram_ctrl_multiple_keys.1865286224 May 14 02:42:39 PM PDT 24 May 14 02:52:16 PM PDT 24 23511078990 ps
T821 /workspace/coverage/default/3.sram_ctrl_lc_escalation.575470725 May 14 02:28:45 PM PDT 24 May 14 02:28:58 PM PDT 24 5180221491 ps
T822 /workspace/coverage/default/37.sram_ctrl_mem_partial_access.1505522995 May 14 02:48:42 PM PDT 24 May 14 02:48:46 PM PDT 24 176465861 ps
T823 /workspace/coverage/default/23.sram_ctrl_access_during_key_req.3531980158 May 14 02:42:05 PM PDT 24 May 14 03:00:21 PM PDT 24 3406403350 ps
T824 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.69205275 May 14 02:53:17 PM PDT 24 May 14 02:57:48 PM PDT 24 16738126433 ps
T825 /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.1484128183 May 14 02:42:49 PM PDT 24 May 14 02:44:01 PM PDT 24 124415113 ps
T826 /workspace/coverage/default/13.sram_ctrl_executable.3229719348 May 14 02:32:47 PM PDT 24 May 14 02:47:23 PM PDT 24 9030305001 ps
T827 /workspace/coverage/default/36.sram_ctrl_access_during_key_req.237328912 May 14 02:47:48 PM PDT 24 May 14 03:03:58 PM PDT 24 4560851419 ps
T828 /workspace/coverage/default/38.sram_ctrl_mem_walk.703292641 May 14 02:49:25 PM PDT 24 May 14 02:49:34 PM PDT 24 139063674 ps
T829 /workspace/coverage/default/31.sram_ctrl_multiple_keys.360864225 May 14 02:44:27 PM PDT 24 May 14 02:59:13 PM PDT 24 9452875656 ps
T830 /workspace/coverage/default/24.sram_ctrl_max_throughput.915820486 May 14 02:42:14 PM PDT 24 May 14 02:43:41 PM PDT 24 119383345 ps
T831 /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2987751957 May 14 02:44:06 PM PDT 24 May 14 02:44:32 PM PDT 24 314578485 ps
T832 /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3060336879 May 14 02:28:38 PM PDT 24 May 14 02:30:11 PM PDT 24 135814888 ps
T833 /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.829736029 May 14 02:31:11 PM PDT 24 May 14 02:36:16 PM PDT 24 8508018811 ps
T834 /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.4087814788 May 14 02:48:16 PM PDT 24 May 14 02:54:11 PM PDT 24 56163252532 ps
T835 /workspace/coverage/default/4.sram_ctrl_max_throughput.571813937 May 14 02:29:02 PM PDT 24 May 14 02:29:10 PM PDT 24 56790465 ps
T836 /workspace/coverage/default/1.sram_ctrl_multiple_keys.979197465 May 14 02:28:26 PM PDT 24 May 14 02:46:27 PM PDT 24 14876608969 ps
T837 /workspace/coverage/default/34.sram_ctrl_mem_partial_access.1382663234 May 14 02:46:38 PM PDT 24 May 14 02:46:46 PM PDT 24 124982839 ps
T838 /workspace/coverage/default/17.sram_ctrl_lc_escalation.1700545729 May 14 02:34:25 PM PDT 24 May 14 02:34:30 PM PDT 24 1864704236 ps
T839 /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1358455865 May 14 02:41:46 PM PDT 24 May 14 02:47:06 PM PDT 24 4468110052 ps
T840 /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.889413883 May 14 02:55:36 PM PDT 24 May 14 02:58:53 PM PDT 24 30934782013 ps
T841 /workspace/coverage/default/22.sram_ctrl_stress_all.2698616485 May 14 02:41:54 PM PDT 24 May 14 03:00:35 PM PDT 24 93304362493 ps
T842 /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1819194892 May 14 02:34:28 PM PDT 24 May 14 02:34:36 PM PDT 24 239563049 ps
T843 /workspace/coverage/default/41.sram_ctrl_ram_cfg.3018812408 May 14 02:51:18 PM PDT 24 May 14 02:51:21 PM PDT 24 48311147 ps
T844 /workspace/coverage/default/6.sram_ctrl_alert_test.982119649 May 14 02:30:02 PM PDT 24 May 14 02:30:03 PM PDT 24 13423193 ps
T845 /workspace/coverage/default/2.sram_ctrl_access_during_key_req.2277951513 May 14 02:28:36 PM PDT 24 May 14 02:28:55 PM PDT 24 271502530 ps
T846 /workspace/coverage/default/38.sram_ctrl_lc_escalation.2523794873 May 14 02:48:58 PM PDT 24 May 14 02:49:04 PM PDT 24 1215039775 ps
T847 /workspace/coverage/default/12.sram_ctrl_executable.521358 May 14 02:32:17 PM PDT 24 May 14 02:32:38 PM PDT 24 1350803144 ps
T848 /workspace/coverage/default/30.sram_ctrl_executable.3600278388 May 14 02:44:07 PM PDT 24 May 14 03:11:38 PM PDT 24 74868770418 ps
T849 /workspace/coverage/default/46.sram_ctrl_mem_walk.2665710875 May 14 02:54:27 PM PDT 24 May 14 02:54:32 PM PDT 24 77172843 ps
T850 /workspace/coverage/default/18.sram_ctrl_smoke.2968420735 May 14 02:34:48 PM PDT 24 May 14 02:34:51 PM PDT 24 408452201 ps
T851 /workspace/coverage/default/14.sram_ctrl_stress_pipeline.1552265500 May 14 02:32:58 PM PDT 24 May 14 02:37:35 PM PDT 24 5881100442 ps
T852 /workspace/coverage/default/17.sram_ctrl_regwen.2190490516 May 14 02:34:26 PM PDT 24 May 14 02:36:17 PM PDT 24 4401833305 ps
T853 /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2441942940 May 14 02:30:22 PM PDT 24 May 14 02:33:46 PM PDT 24 2001805096 ps
T854 /workspace/coverage/default/43.sram_ctrl_max_throughput.274682174 May 14 02:52:06 PM PDT 24 May 14 02:54:43 PM PDT 24 1432159447 ps
T108 /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2781642263 May 14 02:44:45 PM PDT 24 May 14 02:44:58 PM PDT 24 1149080621 ps
T855 /workspace/coverage/default/10.sram_ctrl_lc_escalation.3223500699 May 14 02:31:19 PM PDT 24 May 14 02:31:29 PM PDT 24 3011248121 ps
T856 /workspace/coverage/default/19.sram_ctrl_smoke.3384372000 May 14 02:35:05 PM PDT 24 May 14 02:35:25 PM PDT 24 4171506932 ps
T857 /workspace/coverage/default/3.sram_ctrl_mem_walk.3223675738 May 14 02:28:54 PM PDT 24 May 14 02:29:00 PM PDT 24 237760072 ps
T858 /workspace/coverage/default/22.sram_ctrl_bijection.4195597517 May 14 02:41:43 PM PDT 24 May 14 02:42:38 PM PDT 24 3189759141 ps
T859 /workspace/coverage/default/28.sram_ctrl_ram_cfg.217000888 May 14 02:43:20 PM PDT 24 May 14 02:43:22 PM PDT 24 79596650 ps
T109 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1631270842 May 14 02:46:41 PM PDT 24 May 14 02:46:50 PM PDT 24 241695988 ps
T860 /workspace/coverage/default/5.sram_ctrl_lc_escalation.4038236549 May 14 02:29:38 PM PDT 24 May 14 02:29:47 PM PDT 24 2403745584 ps
T861 /workspace/coverage/default/11.sram_ctrl_mem_walk.3387870188 May 14 02:32:00 PM PDT 24 May 14 02:32:05 PM PDT 24 75311172 ps
T862 /workspace/coverage/default/19.sram_ctrl_multiple_keys.2064624681 May 14 02:35:07 PM PDT 24 May 14 02:50:54 PM PDT 24 14786279692 ps
T863 /workspace/coverage/default/36.sram_ctrl_stress_pipeline.1796917030 May 14 02:47:42 PM PDT 24 May 14 02:52:48 PM PDT 24 3356510126 ps
T864 /workspace/coverage/default/36.sram_ctrl_lc_escalation.1350475036 May 14 02:47:51 PM PDT 24 May 14 02:47:59 PM PDT 24 483466039 ps
T865 /workspace/coverage/default/25.sram_ctrl_ram_cfg.3472356162 May 14 02:42:31 PM PDT 24 May 14 02:42:33 PM PDT 24 27862174 ps
T866 /workspace/coverage/default/0.sram_ctrl_access_during_key_req.3508909913 May 14 02:28:22 PM PDT 24 May 14 02:42:06 PM PDT 24 2831910812 ps
T867 /workspace/coverage/default/40.sram_ctrl_access_during_key_req.2073974602 May 14 02:50:33 PM PDT 24 May 14 03:01:03 PM PDT 24 7670024214 ps
T868 /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2767098040 May 14 02:31:41 PM PDT 24 May 14 02:32:18 PM PDT 24 5162367299 ps
T869 /workspace/coverage/default/11.sram_ctrl_stress_pipeline.1814348007 May 14 02:31:41 PM PDT 24 May 14 02:35:37 PM PDT 24 10995568031 ps
T870 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2795612406 May 14 02:53:27 PM PDT 24 May 14 02:55:16 PM PDT 24 567248475 ps
T871 /workspace/coverage/default/15.sram_ctrl_stress_all.163742797 May 14 02:33:36 PM PDT 24 May 14 03:28:24 PM PDT 24 49331585140 ps
T872 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.4053044233 May 14 02:49:07 PM PDT 24 May 14 02:51:46 PM PDT 24 395331504 ps
T873 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3731057188 May 14 02:52:37 PM PDT 24 May 14 02:57:09 PM PDT 24 49535515180 ps
T874 /workspace/coverage/default/18.sram_ctrl_mem_walk.4043880062 May 14 02:34:57 PM PDT 24 May 14 02:35:09 PM PDT 24 658058626 ps
T875 /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1508275555 May 14 02:41:52 PM PDT 24 May 14 02:43:36 PM PDT 24 8603258538 ps
T876 /workspace/coverage/default/31.sram_ctrl_executable.1305944788 May 14 02:44:37 PM PDT 24 May 14 03:06:10 PM PDT 24 64661889934 ps
T877 /workspace/coverage/default/49.sram_ctrl_partial_access.2414023160 May 14 02:56:08 PM PDT 24 May 14 02:57:11 PM PDT 24 4841177870 ps
T878 /workspace/coverage/default/32.sram_ctrl_mem_partial_access.354316827 May 14 02:45:20 PM PDT 24 May 14 02:45:27 PM PDT 24 153474696 ps
T879 /workspace/coverage/default/23.sram_ctrl_mem_walk.2094321613 May 14 02:41:57 PM PDT 24 May 14 02:42:02 PM PDT 24 77782067 ps
T880 /workspace/coverage/default/25.sram_ctrl_access_during_key_req.2854756311 May 14 02:42:27 PM PDT 24 May 14 02:57:46 PM PDT 24 9357805452 ps
T881 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3769229047 May 14 02:45:14 PM PDT 24 May 14 02:45:17 PM PDT 24 52226832 ps
T882 /workspace/coverage/default/14.sram_ctrl_partial_access.261627602 May 14 02:33:06 PM PDT 24 May 14 02:33:10 PM PDT 24 259909430 ps
T883 /workspace/coverage/default/28.sram_ctrl_access_during_key_req.2558992334 May 14 02:43:09 PM PDT 24 May 14 02:51:17 PM PDT 24 7059169220 ps
T884 /workspace/coverage/default/12.sram_ctrl_stress_all.92227918 May 14 02:32:28 PM PDT 24 May 14 03:02:35 PM PDT 24 27345099047 ps
T885 /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2596038732 May 14 02:29:51 PM PDT 24 May 14 02:32:05 PM PDT 24 146663198 ps
T886 /workspace/coverage/default/8.sram_ctrl_lc_escalation.2859705016 May 14 02:30:33 PM PDT 24 May 14 02:30:37 PM PDT 24 223065580 ps
T887 /workspace/coverage/default/14.sram_ctrl_ram_cfg.1652293560 May 14 02:33:09 PM PDT 24 May 14 02:33:10 PM PDT 24 73909034 ps
T888 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.2580074443 May 14 02:42:52 PM PDT 24 May 14 02:43:00 PM PDT 24 1040112558 ps
T889 /workspace/coverage/default/11.sram_ctrl_alert_test.3308193971 May 14 02:32:00 PM PDT 24 May 14 02:32:01 PM PDT 24 32213652 ps
T890 /workspace/coverage/default/35.sram_ctrl_partial_access.1365197958 May 14 02:46:56 PM PDT 24 May 14 02:47:01 PM PDT 24 267191399 ps
T891 /workspace/coverage/default/13.sram_ctrl_mem_walk.2710097747 May 14 02:32:46 PM PDT 24 May 14 02:32:51 PM PDT 24 159048437 ps
T892 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.3822001067 May 14 02:44:38 PM PDT 24 May 14 02:45:55 PM PDT 24 659529461 ps
T893 /workspace/coverage/default/45.sram_ctrl_bijection.2999270567 May 14 02:53:11 PM PDT 24 May 14 02:54:11 PM PDT 24 956453049 ps
T894 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2627853088 May 14 02:31:56 PM PDT 24 May 14 02:33:26 PM PDT 24 1043714207 ps
T895 /workspace/coverage/default/39.sram_ctrl_stress_pipeline.2570352871 May 14 02:49:41 PM PDT 24 May 14 02:53:45 PM PDT 24 11124847581 ps
T896 /workspace/coverage/default/21.sram_ctrl_smoke.4289008643 May 14 02:36:00 PM PDT 24 May 14 02:36:48 PM PDT 24 162289975 ps
T897 /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.4256167157 May 14 02:42:27 PM PDT 24 May 14 02:49:46 PM PDT 24 13514306659 ps
T898 /workspace/coverage/default/41.sram_ctrl_stress_all.909984677 May 14 02:51:18 PM PDT 24 May 14 03:08:07 PM PDT 24 59405359760 ps
T899 /workspace/coverage/default/9.sram_ctrl_mem_walk.1796052327 May 14 02:31:01 PM PDT 24 May 14 02:31:10 PM PDT 24 141799418 ps
T900 /workspace/coverage/default/20.sram_ctrl_bijection.1706018732 May 14 02:35:34 PM PDT 24 May 14 02:36:01 PM PDT 24 1436432128 ps
T901 /workspace/coverage/default/12.sram_ctrl_ram_cfg.3354122865 May 14 02:32:15 PM PDT 24 May 14 02:32:17 PM PDT 24 47456620 ps
T902 /workspace/coverage/default/24.sram_ctrl_lc_escalation.1519316187 May 14 02:42:14 PM PDT 24 May 14 02:42:20 PM PDT 24 545594044 ps
T903 /workspace/coverage/default/29.sram_ctrl_mem_walk.4289724958 May 14 02:43:39 PM PDT 24 May 14 02:43:46 PM PDT 24 676648738 ps
T904 /workspace/coverage/default/15.sram_ctrl_ram_cfg.3817061807 May 14 02:33:33 PM PDT 24 May 14 02:33:35 PM PDT 24 43957362 ps
T905 /workspace/coverage/default/33.sram_ctrl_stress_pipeline.884535107 May 14 02:45:41 PM PDT 24 May 14 02:50:25 PM PDT 24 7579209366 ps
T906 /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.17132894 May 14 02:35:48 PM PDT 24 May 14 02:36:32 PM PDT 24 109123929 ps
T907 /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.4207803466 May 14 02:29:05 PM PDT 24 May 14 02:36:53 PM PDT 24 18732978556 ps
T908 /workspace/coverage/default/5.sram_ctrl_partial_access.2326265555 May 14 02:29:23 PM PDT 24 May 14 02:29:44 PM PDT 24 3878197288 ps
T909 /workspace/coverage/default/1.sram_ctrl_smoke.1263378308 May 14 02:28:38 PM PDT 24 May 14 02:29:00 PM PDT 24 1065949378 ps
T910 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.1566451712 May 14 02:33:34 PM PDT 24 May 14 02:42:00 PM PDT 24 7205066559 ps
T911 /workspace/coverage/default/31.sram_ctrl_lc_escalation.2245643288 May 14 02:44:39 PM PDT 24 May 14 02:44:45 PM PDT 24 1595790375 ps
T912 /workspace/coverage/default/1.sram_ctrl_alert_test.3180778656 May 14 02:28:38 PM PDT 24 May 14 02:28:43 PM PDT 24 41172729 ps
T913 /workspace/coverage/default/9.sram_ctrl_bijection.632580916 May 14 02:30:52 PM PDT 24 May 14 02:31:51 PM PDT 24 13885700010 ps
T32 /workspace/coverage/default/3.sram_ctrl_sec_cm.1064623531 May 14 02:28:53 PM PDT 24 May 14 02:28:56 PM PDT 24 286386905 ps
T914 /workspace/coverage/default/49.sram_ctrl_executable.1475772148 May 14 02:56:32 PM PDT 24 May 14 03:09:22 PM PDT 24 5159931912 ps
T915 /workspace/coverage/default/35.sram_ctrl_smoke.2282060152 May 14 02:46:47 PM PDT 24 May 14 02:46:52 PM PDT 24 213826081 ps
T916 /workspace/coverage/default/16.sram_ctrl_stress_pipeline.2069433928 May 14 02:33:45 PM PDT 24 May 14 02:39:41 PM PDT 24 3518865020 ps
T917 /workspace/coverage/default/49.sram_ctrl_smoke.4140479484 May 14 02:56:01 PM PDT 24 May 14 02:56:10 PM PDT 24 186907866 ps
T918 /workspace/coverage/default/19.sram_ctrl_ram_cfg.466050448 May 14 02:35:15 PM PDT 24 May 14 02:35:17 PM PDT 24 26434267 ps
T919 /workspace/coverage/default/12.sram_ctrl_multiple_keys.739293490 May 14 02:32:06 PM PDT 24 May 14 02:41:48 PM PDT 24 11402813237 ps
T920 /workspace/coverage/default/8.sram_ctrl_mem_walk.547668763 May 14 02:30:32 PM PDT 24 May 14 02:30:41 PM PDT 24 542320779 ps
T921 /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1246026160 May 14 02:50:57 PM PDT 24 May 14 02:53:35 PM PDT 24 154280663 ps
T922 /workspace/coverage/default/39.sram_ctrl_executable.3125365898 May 14 02:50:00 PM PDT 24 May 14 02:54:53 PM PDT 24 7378013679 ps
T923 /workspace/coverage/default/6.sram_ctrl_partial_access.1066057862 May 14 02:29:52 PM PDT 24 May 14 02:29:57 PM PDT 24 173134871 ps
T924 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.860612775 May 14 02:42:43 PM PDT 24 May 14 02:47:36 PM PDT 24 2992444064 ps
T925 /workspace/coverage/default/40.sram_ctrl_lc_escalation.3837525732 May 14 02:50:29 PM PDT 24 May 14 02:50:37 PM PDT 24 1285534856 ps
T926 /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.2024220718 May 14 02:50:19 PM PDT 24 May 14 02:52:39 PM PDT 24 7631194542 ps
T927 /workspace/coverage/default/39.sram_ctrl_partial_access.1736880993 May 14 02:49:42 PM PDT 24 May 14 02:49:56 PM PDT 24 1620987190 ps
T928 /workspace/coverage/default/14.sram_ctrl_executable.2371532929 May 14 02:33:05 PM PDT 24 May 14 02:56:38 PM PDT 24 3420036369 ps
T929 /workspace/coverage/default/41.sram_ctrl_bijection.1353451525 May 14 02:50:57 PM PDT 24 May 14 02:51:23 PM PDT 24 4664237639 ps
T930 /workspace/coverage/default/49.sram_ctrl_regwen.4066942243 May 14 02:56:34 PM PDT 24 May 14 03:00:08 PM PDT 24 8552525484 ps
T931 /workspace/coverage/default/3.sram_ctrl_mem_partial_access.3218109368 May 14 02:28:54 PM PDT 24 May 14 02:28:58 PM PDT 24 158640309 ps
T932 /workspace/coverage/default/29.sram_ctrl_alert_test.2144448755 May 14 02:43:49 PM PDT 24 May 14 02:43:52 PM PDT 24 12141835 ps
T101 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1216216976 May 14 01:59:27 PM PDT 24 May 14 01:59:31 PM PDT 24 1176569962 ps
T933 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3762729907 May 14 01:58:52 PM PDT 24 May 14 01:58:56 PM PDT 24 73358937 ps
T66 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.945893834 May 14 01:58:53 PM PDT 24 May 14 01:58:56 PM PDT 24 31711643 ps
T67 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.786642730 May 14 01:58:59 PM PDT 24 May 14 01:59:03 PM PDT 24 606911988 ps
T934 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2964560368 May 14 01:59:20 PM PDT 24 May 14 01:59:26 PM PDT 24 193432283 ps
T102 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.148449765 May 14 01:59:08 PM PDT 24 May 14 01:59:11 PM PDT 24 335683589 ps
T68 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.952751732 May 14 01:58:52 PM PDT 24 May 14 01:58:54 PM PDT 24 29697549 ps
T89 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2128102621 May 14 01:59:08 PM PDT 24 May 14 01:59:10 PM PDT 24 22457413 ps
T69 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.4047471145 May 14 01:59:08 PM PDT 24 May 14 01:59:10 PM PDT 24 43095474 ps
T935 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2012750194 May 14 01:59:09 PM PDT 24 May 14 01:59:11 PM PDT 24 150044396 ps
T70 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1841296469 May 14 01:59:00 PM PDT 24 May 14 01:59:02 PM PDT 24 18263498 ps
T103 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2808053727 May 14 01:59:32 PM PDT 24 May 14 01:59:36 PM PDT 24 197650681 ps
T98 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1451050474 May 14 01:59:00 PM PDT 24 May 14 01:59:02 PM PDT 24 12236675 ps
T119 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1689815641 May 14 01:58:51 PM PDT 24 May 14 01:58:54 PM PDT 24 218533171 ps
T71 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2427580435 May 14 01:59:09 PM PDT 24 May 14 01:59:13 PM PDT 24 342177332 ps
T72 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3482284230 May 14 01:59:19 PM PDT 24 May 14 01:59:24 PM PDT 24 426947244 ps
T936 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3412301196 May 14 01:58:52 PM PDT 24 May 14 01:58:55 PM PDT 24 899568386 ps
T937 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3122405533 May 14 01:59:19 PM PDT 24 May 14 01:59:23 PM PDT 24 151662212 ps
T99 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4213131438 May 14 01:59:03 PM PDT 24 May 14 01:59:05 PM PDT 24 30929741 ps
T938 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.83010127 May 14 01:59:01 PM PDT 24 May 14 01:59:07 PM PDT 24 252720219 ps
T100 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.513721016 May 14 01:59:00 PM PDT 24 May 14 01:59:02 PM PDT 24 19367060 ps
T73 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3218144232 May 14 01:59:10 PM PDT 24 May 14 01:59:11 PM PDT 24 19823324 ps
T939 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1798629502 May 14 01:59:26 PM PDT 24 May 14 01:59:28 PM PDT 24 14862599 ps
T74 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.613180095 May 14 01:59:21 PM PDT 24 May 14 01:59:27 PM PDT 24 6080812064 ps
T940 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1033532017 May 14 01:59:21 PM PDT 24 May 14 01:59:25 PM PDT 24 142244336 ps
T75 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.44960908 May 14 01:59:00 PM PDT 24 May 14 01:59:04 PM PDT 24 463439650 ps
T941 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1181324415 May 14 01:59:30 PM PDT 24 May 14 01:59:35 PM PDT 24 690759393 ps
T76 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.260217058 May 14 01:59:11 PM PDT 24 May 14 01:59:12 PM PDT 24 16246781 ps
T942 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1944378434 May 14 01:59:10 PM PDT 24 May 14 01:59:15 PM PDT 24 162880601 ps
T943 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1651351100 May 14 01:59:34 PM PDT 24 May 14 01:59:38 PM PDT 24 85365306 ps
T944 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.293540425 May 14 01:59:31 PM PDT 24 May 14 01:59:33 PM PDT 24 14224395 ps
T90 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3668532947 May 14 01:59:33 PM PDT 24 May 14 01:59:36 PM PDT 24 69934938 ps
T120 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.308552180 May 14 01:59:31 PM PDT 24 May 14 01:59:34 PM PDT 24 109247154 ps
T945 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.938399454 May 14 01:59:40 PM PDT 24 May 14 01:59:44 PM PDT 24 81642040 ps
T91 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2080763303 May 14 01:59:08 PM PDT 24 May 14 01:59:09 PM PDT 24 42853211 ps
T946 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3830877876 May 14 01:59:40 PM PDT 24 May 14 01:59:45 PM PDT 24 102252320 ps
T947 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.564942151 May 14 01:59:40 PM PDT 24 May 14 01:59:42 PM PDT 24 13456986 ps
T122 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.37495230 May 14 01:59:01 PM PDT 24 May 14 01:59:04 PM PDT 24 252036966 ps
T948 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2645092641 May 14 01:59:35 PM PDT 24 May 14 01:59:37 PM PDT 24 25761511 ps
T949 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2216244649 May 14 01:58:59 PM PDT 24 May 14 01:59:02 PM PDT 24 23271700 ps
T950 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1624203998 May 14 01:59:27 PM PDT 24 May 14 01:59:32 PM PDT 24 94464066 ps
T77 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.277407987 May 14 01:59:01 PM PDT 24 May 14 01:59:03 PM PDT 24 61256883 ps
T78 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1424368473 May 14 01:59:32 PM PDT 24 May 14 01:59:36 PM PDT 24 212196886 ps
T951 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3322128872 May 14 01:59:34 PM PDT 24 May 14 01:59:38 PM PDT 24 79225889 ps
T952 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2208879480 May 14 01:59:19 PM PDT 24 May 14 01:59:21 PM PDT 24 66025890 ps
T953 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2945173765 May 14 01:59:33 PM PDT 24 May 14 01:59:35 PM PDT 24 13829095 ps
T115 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.34383972 May 14 01:59:26 PM PDT 24 May 14 01:59:28 PM PDT 24 276671163 ps
T954 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1157444467 May 14 01:59:21 PM PDT 24 May 14 01:59:24 PM PDT 24 115984005 ps
T955 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2949102782 May 14 01:59:27 PM PDT 24 May 14 01:59:30 PM PDT 24 122569438 ps
T956 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1584351930 May 14 01:59:00 PM PDT 24 May 14 01:59:04 PM PDT 24 56832821 ps
T116 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1170303379 May 14 01:59:28 PM PDT 24 May 14 01:59:31 PM PDT 24 157395375 ps
T117 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3081622070 May 14 01:59:03 PM PDT 24 May 14 01:59:06 PM PDT 24 206208161 ps
T121 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3251710347 May 14 01:58:58 PM PDT 24 May 14 01:59:00 PM PDT 24 238023163 ps
T957 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3996620869 May 14 01:58:53 PM PDT 24 May 14 01:58:56 PM PDT 24 85033005 ps
T958 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1668718294 May 14 01:58:59 PM PDT 24 May 14 01:59:01 PM PDT 24 59293465 ps
T959 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.91621171 May 14 01:59:36 PM PDT 24 May 14 01:59:39 PM PDT 24 23982204 ps
T960 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.196095972 May 14 01:59:20 PM PDT 24 May 14 01:59:23 PM PDT 24 181217135 ps
T118 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1855780815 May 14 01:59:11 PM PDT 24 May 14 01:59:14 PM PDT 24 77396748 ps
T79 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1688636131 May 14 01:59:26 PM PDT 24 May 14 01:59:30 PM PDT 24 3088656116 ps
T961 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1372218666 May 14 01:58:51 PM PDT 24 May 14 01:58:53 PM PDT 24 35204207 ps
T962 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3655072369 May 14 01:59:00 PM PDT 24 May 14 01:59:03 PM PDT 24 415938462 ps
T123 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2345505909 May 14 01:59:00 PM PDT 24 May 14 01:59:04 PM PDT 24 540828268 ps
T963 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1913697665 May 14 01:59:25 PM PDT 24 May 14 01:59:29 PM PDT 24 68565872 ps
T964 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.470933954 May 14 01:58:52 PM PDT 24 May 14 01:58:53 PM PDT 24 75495025 ps
T965 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2749948824 May 14 01:59:27 PM PDT 24 May 14 01:59:31 PM PDT 24 328702180 ps
T80 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3725120148 May 14 01:59:25 PM PDT 24 May 14 01:59:29 PM PDT 24 1589878824 ps
T966 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2114518194 May 14 01:59:31 PM PDT 24 May 14 01:59:32 PM PDT 24 79941198 ps
T967 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2527923727 May 14 01:58:58 PM PDT 24 May 14 01:59:00 PM PDT 24 36993248 ps
T87 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3787241981 May 14 01:58:51 PM PDT 24 May 14 01:58:55 PM PDT 24 915160076 ps
T127 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1030701251 May 14 01:59:25 PM PDT 24 May 14 01:59:29 PM PDT 24 592504178 ps
T968 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.280740544 May 14 01:59:36 PM PDT 24 May 14 01:59:40 PM PDT 24 779973596 ps
T969 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3985577954 May 14 01:58:52 PM PDT 24 May 14 01:58:54 PM PDT 24 17777839 ps
T970 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2714066040 May 14 01:59:26 PM PDT 24 May 14 01:59:28 PM PDT 24 28684332 ps
T971 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3195060783 May 14 01:59:09 PM PDT 24 May 14 01:59:13 PM PDT 24 84338225 ps
T972 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3293915727 May 14 01:59:23 PM PDT 24 May 14 01:59:25 PM PDT 24 123905135 ps
T973 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.273207257 May 14 01:59:10 PM PDT 24 May 14 01:59:14 PM PDT 24 1737640901 ps
T974 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1072892643 May 14 01:59:01 PM PDT 24 May 14 01:59:06 PM PDT 24 43233877 ps
T975 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3471982869 May 14 01:59:25 PM PDT 24 May 14 01:59:27 PM PDT 24 33024509 ps
T976 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1811132005 May 14 01:59:37 PM PDT 24 May 14 01:59:40 PM PDT 24 27945620 ps
T977 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1765326174 May 14 01:59:08 PM PDT 24 May 14 01:59:13 PM PDT 24 1979166356 ps
T978 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.935323206 May 14 01:59:09 PM PDT 24 May 14 01:59:13 PM PDT 24 226689209 ps
T979 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1722615384 May 14 01:58:49 PM PDT 24 May 14 01:58:51 PM PDT 24 28417415 ps
T980 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3932423109 May 14 01:59:28 PM PDT 24 May 14 01:59:30 PM PDT 24 17318015 ps
T981 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1569393067 May 14 01:59:01 PM PDT 24 May 14 01:59:06 PM PDT 24 1425544132 ps
T126 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.810119119 May 14 01:59:33 PM PDT 24 May 14 01:59:37 PM PDT 24 754455956 ps
T982 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2216706476 May 14 01:58:52 PM PDT 24 May 14 01:58:55 PM PDT 24 282084431 ps
T983 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2590792385 May 14 01:59:42 PM PDT 24 May 14 01:59:43 PM PDT 24 18653047 ps
T984 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1189403821 May 14 01:58:52 PM PDT 24 May 14 01:58:55 PM PDT 24 54599365 ps
T985 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3106053934 May 14 01:59:08 PM PDT 24 May 14 01:59:09 PM PDT 24 50144782 ps
T986 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2698710043 May 14 01:58:59 PM PDT 24 May 14 01:59:02 PM PDT 24 173374524 ps
T987 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1605175996 May 14 01:59:26 PM PDT 24 May 14 01:59:29 PM PDT 24 74383494 ps
T988 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.512627875 May 14 01:59:27 PM PDT 24 May 14 01:59:31 PM PDT 24 31247631 ps
T989 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.861725327 May 14 01:59:31 PM PDT 24 May 14 01:59:34 PM PDT 24 35027759 ps
T990 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.286128212 May 14 01:59:33 PM PDT 24 May 14 01:59:35 PM PDT 24 17341320 ps
T991 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.756028851 May 14 01:59:32 PM PDT 24 May 14 01:59:36 PM PDT 24 48287504 ps
T992 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.873698198 May 14 01:59:08 PM PDT 24 May 14 01:59:10 PM PDT 24 28493464 ps
T993 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3083219091 May 14 01:59:07 PM PDT 24 May 14 01:59:09 PM PDT 24 14515813 ps
T994 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3469085981 May 14 01:59:19 PM PDT 24 May 14 01:59:21 PM PDT 24 31709840 ps
T995 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.210728136 May 14 01:59:31 PM PDT 24 May 14 01:59:35 PM PDT 24 277696783 ps
T996 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2227842985 May 14 01:59:11 PM PDT 24 May 14 01:59:15 PM PDT 24 868277786 ps
T997 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3258351501 May 14 01:59:00 PM PDT 24 May 14 01:59:03 PM PDT 24 27562579 ps
T998 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3831800365 May 14 01:59:31 PM PDT 24 May 14 01:59:33 PM PDT 24 134884731 ps
T999 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2595511359 May 14 01:59:26 PM PDT 24 May 14 01:59:28 PM PDT 24 112896975 ps
T1000 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2891210130 May 14 01:58:53 PM PDT 24 May 14 01:58:58 PM PDT 24 385965742 ps
T1001 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.71128020 May 14 01:59:26 PM PDT 24 May 14 01:59:30 PM PDT 24 182407550 ps
T125 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2091664453 May 14 01:59:09 PM PDT 24 May 14 01:59:13 PM PDT 24 232120599 ps
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