Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	154482304	1			T1	6266		T2	78954		T3	475422
instr_valid_dis	120570283	1			T1	6266		T2	78954		T3	475422
instr_en	24272919	1			T5	125490		T12	73176		T16	31084

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11144413	1			T5	61154		T12	182064		T16	30948
sram_ifetch_valid_disable	120142827	1			T1	6266		T2	78954		T3	475422
sram_ifetch_enable	23195064	1			T5	250526		T12	371792		T16	55048

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	154482304	1			T1	6266		T2	78954		T3	475422
hw_debug_en_valid_off	118530956	1			T1	6266		T2	78954		T3	475422
hw_debug_en_on	23711261	1			T5	251770		T12	353068		T16	55048

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	120142827	1			T1	6266		T2	78954		T3	475422
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	107343706	1			T1	6266		T2	78954		T3	475422
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9279187	1			T5	54920		T12	35850		T16	136
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4340726	1			T12	78262		T16	30948		T64	40936
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1478538	1			T12	48326		T27	43840		T147	732
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2068026	1			T16	30948		T64	40936		T27	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4396383	1			T5	43118		T12	78208		T27	35512
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1564329	1			T12	60574		T27	33114		T29	27242
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1959894	1			T5	43118		T12	17634		T27	2398
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10713931	1			T5	109026		T12	81782		T64	74814
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	5714316	1			T5	20068		T12	40912		T27	61474
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3496643	1			T5	54920		T12	35850		T64	59870

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9990070	1			T5	27452		T12	19692		T64	37170
lc_exec_en	8600947	1			T5	99626		T12	193078		T16	55048
valid_exec_dis	114791546	1			T1	6266		T2	78954		T3	475422
invalid_exec_dis	34339477	1			T5	311680		T12	553856		T16	85996